Using Packed Registers in Stratix V ALM

[Altera_Forum]

I dont seem to be able to get Quartus to use the extra Registers available in the Stratix V ALM, this would help a great deal in my pipelined design. 

Am I missing a special option or setting?  This simple program is an XOR gate followed by two registers, and it looks like Stratix V should be able to use the two output registers to implement this by feeding the output of the first register back round into the datae/dataf inputs. (The first register only feeds the second, and both have the same reset, clock).   When I assign this to a LogicLock region of 1 LAB I get "LogicLock region is too small to contain its members".

[Altera_Forum]

Could it be your xor takes more luts than you have in one LAB. we are talking about 16 x 2 registers as well 

By the way, register connection back to back does not do much for fmax apart from delay. Pipelining refers to breaking comb paths by inserting register to cut it shorter into two segments.

[Altera_Forum]

The Xor should be bitwise so 16 2luts should definitely fit. 

The registers are needed to balance the pipeline delay (when used in the bigger design), So this wasn't really meant for speed - just reduces the area in a wide datapath. Should still pack though I think?