Hi FPGA community,
We need to simulate our FPGA design post synthesis (VO file).
In QUARTUS 18.1 we used the following TCL commands:
set_global_assignment -name EDA_SIMULATION_TOOL "Xcelium-Verilog (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR simulation/xcelium -section_id eda_simulation
set_global_assignment -name SEARCH_PATH "/home1/softDir/cds_xcelium2003/tools/methodology/UVM/CDNS-1.2/sv/src/"
set_global_assignment -name SEARCH_PATH "/home1/softDir/cds_xcelium2003/tools/methodology/UVM/CDNS-1.2/additions/sv/"
Then after successfully compilation, QUARTUS created the folder
simulation/xcelium and in this folder a simulation file .vo has been created.
But with QUARTUS 20.4, this does not work any more. QUARTUS does not create the simulations folder!
Does any body has any idea, how to generate the simulation file vo (verilog output file) in QUARTUS PRIME PRO 20.4?
Were you using Quartus Prime Pro 18.1 before this? I suspect your problem arose due to Quartus failing to recognise the Xcelium executable path.
Refer to this KDB for workaround: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/...
We did not receive any response to the previous reply provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.