Using fpga to implement long length FFT

[Altera_Forum]

Hello Guys, 

 I got a long length data, and want to convert the data from time domain to frequency domain. These data from ADC, the sampling frequrency is 20MHz, and sampling time is about several seconds. So the data numbers are more than serval million. My question is how to convert it to frequency domain by using Altera's FFT Mega-core? Actually, is how to select my FFT's length?  Thanks  Best Regard  Jerry

[Altera_Forum]

use a suitable resolution. fft does not need to be same size as a chunk of data.

[Altera_Forum]

--- Quote Start ---  use a suitable resolution. fft does not need to be same size as a chunk of data.  --- Quote End ---    Dear kaz,  Thanks for you quickly reply! "suitable resolution" means i just need to select reasonable FFT length, which can recognize all signal frequency spectrum i concern. Am i right?  BTW, which IO type i should use in this case?  Thanks  Jerry

[Altera_Forum]

yes you are right. 

which IO? I have absolutely no idea

[Altera_Forum]

--- Quote Start ---  yes you are right. which IO? I have absolutely no idea  --- Quote End ---    Hi kaz, I'm sorry to confuse you, i mean which I/O data flow i should select for this application?  For FFT application, i saw someone else's project, who converted the ADC's data to signed value, is this necessary?  Thanks

[Altera_Forum]

--- Quote Start ---  Hi kaz, I'm sorry to confuse you, i mean which I/O data flow i should select for this application?  For FFT application, i saw someone else's project, who converted the ADC's data to signed value, is this necessary?  Thanks  --- Quote End ---    your fft ip should tell you. Normally ADC data that represents a signal swings around zero (no dc) if in 2's complement. But it could be using offset binary which needs inverting the sign bit.  At HDL level I expect std_logic_vector type.

[Altera_Forum]

--- Quote Start ---  your fft ip should tell you. Normally ADC data that represents a signal swings around zero (no dc) if in 2's complement. But it could be using offset binary which needs inverting the sign bit.  At HDL level I expect std_logic_vector type.  --- Quote End ---    I see, maybe their analog signal just as you said around zero. however, the negative value is no sense for our system. so our system the signal is from 0~1000 mv, instead of -500~500 mV.  BTW, i have another question need you guidance: the ADC sample clock is 20 MHz, but my system clock is 100 MHz, do i synchronize the samples from 20 MHz into 100 MHz firstly(FFT run at 100 MHz, and i think this will save process time) or synchronize the FFT's out from 20 MHz to 100 MHz(FFT run at 20 MHz )? Which one is better for our application? Will each of above process affect the frequency spectrum analysis?

[Altera_Forum]

the voltage range you mentioned is the analogue side of ADC. The digital values could be +/-, see the ADC data sheet. 

 if ADC clock is 20MHz (and sampling rate is 20Msps) but system clock is 100MHz then your fft should tell if it supports time folding to reduce resource. In any case the system clock and data clock must be synchronised or clock domains crossed safely(dc fifo).

[Altera_Forum]

--- Quote Start ---  the voltage range you mentioned is the analogue side of ADC. The digital values could be +/-, see the ADC data sheet.  if ADC clock is 20MHz (and sampling rate is 20Msps) but system clock is 100MHz then your fft should tell if it supports time folding to reduce resource. In any case the system clock and data clock must be synchronised or clock domains crossed safely(dc fifo).  --- Quote End ---    I think my purpose is decreasing fft process time, instead of saving resource. And i worry that which would affect the FFT result, could i get a result which is what i don't need?