VCDs of Modelsim and Active-HDL comparison

[Altera_Forum]

Hello. 

 I need to compare value change dump files of different EDA vendors, say Mentor and Aldec.  I've written the simplest test bench:  

1. `timescale 1ns / 100ps //  
2. `define PERIOD_OF_CLK 10 // 100mhz => 10ns with respect to timebase (1ns)  
3. `define HALF_PERIOD_OF_CLK (`PERIOD_OF_CLK / 2)  
4. `define END_TIME 50 // 50ns  
5. module test_tb;  
6. reg clk_tb = 1'b0;   
7. initial begin  
8. $dumpfile("test_tb.vcd");  
9. $dumpvars( 1, clk_tb);  
10. end  
11. initial begin  
12. #0 clk_tb = 1'b0;  
13. forever  
14. #`HALF_PERIOD_OF_CLK clk_tb = !clk_tb;  
15. end  
16. initial begin  
17. #`END_TIME $finish;  
18. end  
19. endmodule  

  And simulated it with Modelsim (Questa) and Active-HDL. Their results' comparison is attached to the post.  Could someone give me an idea why those vcds are different (I mean line# 37:# 500 of Active-HDL - this line is absent in Modelsim's vcd and line# 14:# 0 of Modelsim's vcd which is absent in Active-HDL's vcd)?