VHDL Function Overloading not working

[James_B]

I have a VHDL function that is overloaded and works "inconsistently" meaning that sometimes is works and sometimes is just does not.

The general signature of this function is (with return types as overloaded) : 

     bits(integer, size of result reg) return signed | unsigned | slv

This should work, according to the Quartus handbook which states that subprogram overloading is supported. 

I am using Quartus Prime Standard 20.1 for this project, and code snippet is shown below. 

Basically, if I initialize a register with some sample code such as: 

signed_reg <= bits(500, 16) ; 

or 

unsigned_reg <= bits(800,16); 

or 

slv_reg <= bits(250, 16); 

I get inconsistent results (without Timing Errors in Quartus) for the register initializations. 

I often get for example (showing results in decimal)

signed_reg = 550; 

unsigned_reg = 820;

slv_reg = 260; 

This is unexplained.

The actual package code is shown below. 

Any suggestion or comments are appreciated. 

Thanks. James

 

[Nurina]

Hi,

You need to program it such a way that Quartus knows which bits function to use. The parameter types for all the bits function are the same, try put different parameter types so that Quartus can differentiate the overloaded functions.

For example the TO_INTEGER functions are overloaded in the NUMERIC_STD library like so:

function TO_INTEGER ( ARG: UNSIGNED) return NATURAL;

-- Result subtype: NATURAL. Value cannot be negative since parameter is an

-- UNSIGNED vector.

-- Result: Converts the UNSIGNED vector to an INTEGER.

-- Id: D.2

function TO_INTEGER ( ARG: SIGNED) return INTEGER;

-- Result subtype: INTEGER

-- Result: Converts a SIGNED vector to an INTEGER.

BTW the to_unsigned function takes in arguments that aren't declared as integers like so: TO_UNSIGNED ( ARG,SIZE: NATURAL)

Not sure why you use std_logic_vector(TO_UNSIGNED(L, S)) ? Why can't you just use TO_STDLOGICVECTOR?

You can refer here for the conversion functions: https://www.csee.umbc.edu/portal/help/VHDL/packages/numeric_std.vhd

Regards,

Nurina

[James_B · Accepted solution]

Nurina,

Thank you for the feedback, this is very helpful. 

Basically, if I can summarize your answer, the overloading functions need to have distinct Types for the arguments. From a function signature point of view: 

my_function(arg1 : type1) return result type 1

should have an overloaded function type of : 

my_function(arge1 : type2) return result type 2

Correct ? 

On a background note: 

I am updating a code base that someone else developed; I typically would not use overloaded functions. The design intent was to make the VHDL more readable; however I think the basic issue is that the same argument type is present in all three overloaded versions of the function, as you have illustrated. The design is large and there are many functions in packages meant to make the design more readable, however, there are always issues with VHDL conversions if one does not handle them carefully as appears to be the case here. 

Thank you and Regards,

James

[Nurina]

Hello James,

Yes you're understanding it correctly. Do you have any more questions?

Regards,

Nurina

[James_B]

Nurina, 

Thanks for confirming. I don't have any more questions. 

Thank you for your help. 

Kind Regards, James

[Nurina]

Hi James,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Regards,
Nurina

P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!