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VHDL Quartus Simulation, Libraries and Packages

Hello,

I have:

  • an entity that implements a circuit for parity check: it have as input an 8 bit std_logic_vector and an std_logic as output. It is located in the folder: C:\User\Desktop\Conversioni_di_Tipo\ParityChecker\ParityChecker.vhd

 

  • a function that converts a char in an 8 bit standard_logic_vector, defined in a package, located in the folder:  C:\Users\Desktop\Conversioni_di_Tipo\myLibrary_1\ema_conversion_pkg.vhd

 

  • a testbench which have that entity as DUT but that also uses the conversion function in the package. It is located in the folder:  C:\Users\Desktop\Conversioni_di_Tipo\ParityChecker\simulation\modelsim\ParityChecker_tb.vhd

 

The Quartus project is located in the folder:   C:\Users\\Desktop\Conversioni_di_Tipo\ParityChecker

The file added to the project is the ParityChecker.vhd (it is obviously the top-level entity).

The simulator is ModelSim-Altera.

The testbench file ParityChecker_tb.vhd is set in Assegniment --> Setting --> Simulation --> TestBenches...

 

I start the Analysis & Elaboration that go correctly to the end.

Then, I start RTL simulation, ModelSim open but an it gives these errors because it doesn’t find the package.

 

# Reading pref.tcl

# do ParityChecker_run_msim_rtl_vhdl.do

# if {[file exists rtl_work]} {

#          vdel -lib rtl_work -all

# }

# vlib rtl_work

# vmap work rtl_work

# Model Technology ModelSim - Intel FPGA Edition vmap 2020.1 Lib Mapping Utility 2020.02 Feb 28 2020

# vmap work rtl_work

# Copying C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini

# Modifying modelsim.ini

#

# vcom -93 -work work {C:/Users//Desktop/Conversioni_di_Tipo/ParityChecker/ParityChecker.vhd}

# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020

# Start time: 17:36:37 on Nov 18,2020

# vcom -reportprogress 300 -93 -work work C:/Users//Desktop/Conversioni_di_Tipo/ParityChecker/ParityChecker.vhd

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Compiling entity ParityChecker

# -- Compiling architecture Behavioral of ParityChecker

# End time: 17:36:38 on Nov 18,2020, Elapsed time: 0:00:01

# Errors: 0, Warnings: 0

#

# vcom -93 -work work {C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd}

# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020

# Start time: 17:36:40 on Nov 18,2020

# vcom -reportprogress 300 -93 -work work C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd

# -- Loading package STANDARD

# -- Loading package TEXTIO

# -- Loading package std_logic_1164

# -- Loading package NUMERIC_STD

# ** Error: C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd(5): (vcom-1598) Library "mylibrary_1" not found.

# ** Error: C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd(6): (vcom-1136) Unknown identifier "myLibrary_1".

# ** Note: C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd(8): VHDL Compiler exiting

# End time: 17:36:40 on Nov 18,2020, Elapsed time: 0:00:00

# Errors: 2, Warnings: 0

# ** Error: C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vcom failed.

# Error in macro ./ParityChecker_run_msim_rtl_vhdl.do line 10

# C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vcom failed.

#     while executing

# "vcom -93 -work work {C:/Users/Desktop/Conversioni_di_Tipo/ParityChecker/simulation/modelsim/ParityChecker_TB.vhd}"

 

Could you help me to understand how the libraries have to be handle in a corret manner, especially when user file (needed in a simulation) are arbitrarly located in the PC?

Thank you.

 

Here you can see the file discussed above.

 

 

----------------------------------------------------------------------------------------------------------

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

-----------------------------------------------------

ENTITY ParityChecker IS

   GENERIC (oddParity: STD_LOGIC := '1');     -- ='1' per rilevare la parità dISpari

   PORT ( x : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

           y : OUT STD_LOGIC);

END ParityChecker;

 

ARCHITECTURE Behavioral OF ParityChecker IS

 

BEGIN

   PROCESS (x) IS

      VARIABLE y_var:   STD_LOGIC;

   begIN

      y_var := NOT(oddParity);

      for i IN x'RANGE LOOP

         y_var := y_var XOR x(i);

      END LOOP;

      y <= y_var;

   END PROCESS;

END Behavioral;

----------------------------------------------------------------------------------------------------------

 

 

----------------------------------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

------------------------------------------------

package ema_conversions_pkg is

             function            char_to_slv       (signal charIN: character; constant bitwidth: natural) return std_logic_vector;

end package ema_conversions_pkg;

------------------------------------------------

package body ema_conversions_pkg is

            function            char_to_slv       (signal charIN: character; constant bitwidth: natural) return std_logic_vector is

                        begin

                                    return std_logic_vector(to_unsigned(CHARACTER'POS(charIN), bitwidth));

            end function char_to_slv;

end package body ema_conversions_pkg;

----------------------------------------------------------------------------------------------------------

 

 

----------------------------------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.numeric_std.all;

library myLibrary_1;

use myLibrary_1.ema_conversions_pkg.all;

----------------------------------------------------------------------------------

entity ParityChecker_TB is

end ParityChecker_TB;

----------------------------------------------------------------------------------

architecture Behavioral of ParityChecker_TB is

   signal y_tb: std_logic;

   signal charIN: character;

   signal x_tb: std_logic_vector(7 downto 0);

begin

x_tb <= char_to_slv(charIN,8);

DUT:  entity work.ParityChecker

        generic map('1')         -- ='1' per rilevare la parità dispari,  ='0' per rilevare la parità pari

        port map(x_tb, y_tb);

STIM:   process is

        begin

           charIN <= 'a';

           wait for 20 ns;

           charIN <= 'c';

           wait for 20 ns;

           charIN <= 'F';

           wait;

        end process;

 end Behavioral;

----------------------------------------------------------------------------------------------------------

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