Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Timing Designer Inter-Path-Competition in Nios sub-system

CWarr1
Beginner
‎01-04-2021 04:37 AM
788 Views

Timing designer is reporting 'Inter-Path-Competition' issues for my Arria-10 FPGA design. The path that is highlighted is between the Nios processor and its associated onchip memory. Since both modules are created and connected within Platform Designer, I can not see how to duplicate the specified nodes.
Can anyone suggest how I might resolve this error?
Thanks!

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sstrell
Honored Contributor III
‎01-04-2021 02:32 PM
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Can you show the error?  Timing info from the Timing Analyzer?  Need more details here.

I'm not sure what the "Timing Designer" is.  Do you mean the Design Assistant and you're failing a rule or something?

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CWarr1
Beginner
‎01-05-2021 08:19 AM
766 Views
In response to sstrell

Apologies - I meant Timing Analyzer, not Timing Designer!

I will close this request and re-post with a corrected title

In response to sstrell
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