Timing designer is reporting 'Inter-Path-Competition' issues for my Arria-10 FPGA design. The path that is highlighted is between the Nios processor and its associated onchip memory. Since both modules are created and connected within Platform Designer, I can not see how to duplicate the specified nodes.
Can anyone suggest how I might resolve this error?
Can you show the error? Timing info from the Timing Analyzer? Need more details here.
I'm not sure what the "Timing Designer" is. Do you mean the Design Assistant and you're failing a rule or something?