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Hello everyone, working on a class assignment and am struggling with VHDL syntax. I am getting the following error:
Error (10500): VHDL syntax error at SM_VHDL.VHD(79) near text "ELSE"; expecting ";" So I know my issues has to do with my declaration of Z or Q. This is a state-machine implementation with the following equations state equations:- Q1+ = X1*X0 + Q1*X1
- Q2+ = |X1*|X0 + Q0*|X0
- Z = Q1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;
ENTITY SM_VHDL IS -- Do not modify this entity statement!
PORT(X : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
RESETN,
CLOCK : IN STD_LOGIC;
Z : OUT STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) );
END SM_VHDL; -- Do not modify this entity statement!
ARCHITECTURE behavior of SM_VHDL IS
TYPE STATE_TYPE IS (A, B, C);
SIGNAL state : STATE_TYPE;
BEGIN
PROCESS(CLOCK, RESETN)
BEGIN
IF RESETN = '0' THEN
state <= A;
ELSIF CLOCK'EVENT AND CLOCK = '1' THEN
CASE state IS
WHEN A =>
CASE X IS
WHEN "00" =>
state <= B;
END CASE;
CASE X IS
WHEN "01" =>
state <= A;
END CASE;
CASE X IS
WHEN "10" =>
state <= A;
END CASE;
CASE X IS
WHEN "11" =>
state <= C;
END CASE;
WHEN B =>
CASE X IS
WHEN "00" =>
state <= B;
END CASE;
CASE X IS
WHEN "01" =>
state <= A;
END CASE;
CASE X IS
WHEN "10" =>
state <= B;
END CASE;
CASE X IS
WHEN "11" =>
state <= C;
END CASE;
WHEN C =>
CASE X IS
WHEN "00" =>
state <= B;
END CASE;
CASE X IS
WHEN "01" =>
state <= A;
END CASE;
CASE X IS
WHEN "10" =>
state <= C;
END CASE;
CASE X IS
WHEN "11" =>
state <= C;
END CASE;
END CASE;
END IF;
END PROCESS;
Z <= '1' WHEN state = A ELSE '0';
Q <= "00" WHEN state = A ELSE "01" ELSE "10";
END behavior;
This is the format that was given by the way:
Z <= '1' WHEN ... ELSE ...;
Q <= "00" WHEN ... ELSE ... ELSE ...
Any help getting this compiled, and furthering my understanding would be greatly appreciated.
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Hi
Q <= "00" WHEN ... ELSE ... else ... :oops: You should write
Q <= "00" WHEN ... ELSE
... WHEN ... ELSE
...;
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Thanks, I have changed it to this:
Z <= '1' WHEN state = A ELSE '0';
Q <= "00" WHEN state = A ELSE
"01" WHEN state = B ELSE
"10" WHEN state = C;
And I am now getting the following errors: Error (10313): VHDL Case Statement error at SM_VHDL.VHD(25): Case Statement choices must cover all possible values of expression. Each case takes into account all 4 binary combinations however... Hmm.
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Update: Solved it, I had superfluous code in my case statements. Compiling now. Thanks for your assistance:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.All;
ENTITY SM_VHDL IS -- Do not modify this entity statement!
PORT(X : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
RESETN,
CLOCK : IN STD_LOGIC;
Z : OUT STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) );
END SM_VHDL; -- Do not modify this entity statement!
ARCHITECTURE behavior of SM_VHDL IS
TYPE STATE_TYPE IS (A, B, C);
SIGNAL state : STATE_TYPE;
BEGIN
PROCESS(CLOCK, RESETN)
BEGIN
IF RESETN = '0' THEN
state <= A;
ELSIF CLOCK'EVENT AND CLOCK = '1' THEN
CASE state IS
WHEN A =>
CASE X IS
WHEN "00" =>
state <= B;
WHEN "01" =>
state <= A;
WHEN "10" =>
state <= A;
WHEN "11" =>
state <= C;
END CASE;
WHEN B =>
CASE X IS
WHEN "00" =>
state <= B;
WHEN "01" =>
state <= A;
WHEN "10" =>
state <= B;
WHEN "11" =>
state <= C;
END CASE;
WHEN C =>
CASE X IS
WHEN "00" =>
state <= B;
WHEN "01" =>
state <= A;
WHEN "10" =>
state <= C;
WHEN "11" =>
state <= C;
END CASE;
END CASE;
END IF;
END PROCESS;
Z <= '1' WHEN state = A ELSE '0';
Q <= "00" WHEN state = A ELSE
"01" WHEN state = B ELSE
"10" WHEN state = C;
END behavior;
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