Hi All,I'm receiving the following error message while my VHDL code compilation (actually the compilation has passed, this error appears during load_design):
# ** Warning: (vsim-8523) Cannot reference the signal "/tb_bit_mgr_wrp/i_bit_mgr_wrp/i_bit_mgr/i_filter/gen_flt(0)/gen_flr_cnt/i_flr_cnt/flr_cnt" before it has been elaborated.# Time: 0 ps Iteration: 0 Instance: /tb_bit_mgr_wrp/i_bit_mgr_wrp File: D:/units/bit/rtl/inst/bit_mgr_wrp.vhdHere is an alias, which I used:
alias flr_cnt0_al is <<signal .tb_bit_mgr_wrp.i_bit_mgr_wrp.i_bit_mgr.i_filter.gen_flt(0).gen_flr_cnt.i_flr_cnt.flr_cnt : integer range 0 to FLR_CNT_TRSH>>;What's the problem? The simulator "complains" that it cannot reference the signal before it has been elaborated. How to solve? How to elaborate in this case? Note: I'm using QuestaSim 10.4 Thank you!
As far as I know, an alias is another name for a vhdl signal in the same entity, you create an alias for a signal based on the hierarchy. The compiler only knows the path to a signal after it has elaborated your design, hence the error.
OK, in some place on the web I have read that the alias should be declared after an instance it refers to. This way the signal will be elaborated before it's referenced.But how to do so? It's not possible to put an alias declaration inside of the process. Is there a way to declare an alias in the architecture body after instantiation of the referenced entity?
An alias can be placed anywhere. So an alias to a signal can be declared in a architecture, process, procedure or any other declarative region.Because you must declare them after the entity declaration, you are basically forced to declare them inside processes.
The alias is scoped like anything else. If you create an alias in a process, then it is only available inside that process. BUT, you can use external names to access these from outside the process.Also remember you can declare signals inside a generate, so you could do this:
mygen : if true generate alias a is << something >>; begin -- alias now visible throughout generate end generate mygen;
Also, you can alias an alias, but and alias takes the form of the thing its aliasing. So an alias to a signal is a signal, alias to a variable is a variable etc.