VHDL code help!

[Altera_Forum]

Hi guys, 

 I have written out this code, but it gave me error that type R1-R5 is incompatible with A-E. Please help !!!

[Altera_Forum]

All of the A-E inputs are a single std_logic. 

R1-R8 are declared as integers.   I dont really know what you're trying to do? why not just input a load of integers?

[Altera_Forum]

--- Quote Start ---  All of the A-E inputs are a single std_logic. R1-R8 are declared as integers.   I dont really know what you're trying to do? why not just input a load of integers?  --- Quote End ---    Is there anyway to declare A-E as integer, or vice versa?

[Altera_Forum]

Yes 

 A : In integer;

[Altera_Forum]

--- Quote Start ---  Yes  A : In integer;  --- Quote End ---    Then for the test bench code, the auto generated code still has this  signal A : std_logic := '0';  signal B : std_logic := '0';  signal C : std_logic := '0';  signal D : std_logic := '0';  signal E : std_logic := '0';  How do i change them?

[Altera_Forum]

Please post your modifed code. 

The fact the auto-generated testbench still uses std logic makes me beleive you modified nothing.  And you shouldnt need to use the auto-generation - you can write it yourself.

[Altera_Forum]

--- Quote Start ---  Please post your modifed code. The fact the auto-generated testbench still uses std logic makes me beleive you modified nothing.  And you shouldnt need to use the auto-generation - you can write it yourself.  --- Quote End ---     I modified them manually, and it does not give me errors after i synthesized, so i believe its working? Can teach me how to write test bench manually without auto generated code?

[Altera_Forum]

and i gave me this warnings too  

 Xst:647 - Input <A<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <B<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <C<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <D<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. WARNING:Xst:647 - Input <E<31:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

[Altera_Forum]

This is because you declared the ports as integer without a range definition. integers will synthesise to 32 bit busses, and as the MSBs are never used, they are removed. 

 You should not use integers at the top level to connect to pins on the device.  There are plenty of tutorials on the internet on how to write a testbench. A testbench is just another peice of code (maybe VHDL) that provides stimulus for your design under test. Because it is not synthesised, you can write things you cannot write in VHDL code for FPGAs, eg:   signal clk : std_logic := '0'; .... clk <= not clk after 5 ns; --100 MHz

[Altera_Forum]

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[Altera_Forum]

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