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VHDL error - natural type does not match string literal

Altera_Forum
Honored Contributor II
11,979 Views

Hi, 

 

I am trying to make a simple program which will turn on the green LED when the Key(0) is pressed and when we leave the key, it will be switched off.  

 

I am getting this error in the code for some reason though - 

Error (10515): VHDL type mismatch error at pract.vhd(36): natural type does not match string literal 

 

 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.std_logic_arith.all; 

use ieee.numeric_std.all; 

use ieee.std_logic_unsigned.all; 

 

entity pract is  

port ( 

iKEY : in std_logic_vector(0 downto 0); 

oLEDG: out std_logic_vector(2 downto 0) 

); 

end entity pract; 

 

architecture behav of pract is  

 

signal sel : std_logic_vector(0 downto 0) := "0"; 

begin  

 

 

p1 : process(iKEY) 

begin 

 

if(rising_edge(iKEY(0))) then 

sel <= sel + "1"; 

end if; 

 

end process; 

 

p2 : process(iKEY)  

begin 

 

case sel is  

when "0" => 

oledg("000") <= '0'; -- this is where i get the error 

when "1" => 

oLEDG("000") <= '1'; 

end case; 

 

end process; 

 

end behav;
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Altera_Forum
Honored Contributor II
8,940 Views

Your output is 3-bits 

 

oLEDG: out std_logic_vector(2 downto 0) 

 

you need to assign a 3-bit value, eg., 

 

oLEDG <= "111"; 

 

or  

 

oLEDG <= "000"; 

 

If you want to just assign to 1-bit, lets say bit 0, then you can do 

 

oLEG(0) <= '1'; 

 

Note that '1' is a 1-bit std_logic value, and "111" is a 3-bit std_logic_vector value. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
8,940 Views

Hey, 

 

I edited the code but I have the same error -  

Error (10515): VHDL type mismatch error at pract.vhd(36): natural type does not match string literal 

Error (10515): VHDL type mismatch error at pract.vhd(36): std_ulogic type does not match string literal 

 

 

case sel is  

when "0" => 

oLEDG("000") <= "000"; 

when "1" => 

oLEDG("000") <= "111"; 

end case;
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Altera_Forum
Honored Contributor II
8,940 Views

Look at my code again, then look at your code ... what did you forget to change? Hint, what is to the left of <=.

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Altera_Forum
Honored Contributor II
8,940 Views

Thank you very much. It works :D

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Altera_Forum
Honored Contributor II
8,940 Views

Never use these libs BOTH: 

use ieee.std_logic_arith.all; 

use ieee.numeric_std.all; 

 

Better use only numeric_std instead.
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