VHDL need some help in coding

[Altera_Forum]

A system has a 3-bit input D_IN which is read in at every positive going edge of a clock input CLK. If the current D_IN is greater than the previous D_IN by at least 2, a 3-bit output COUNT is incremented. If D_IN is 0 for 3 consecutive CLK cycles, the COUNT is reset. When COUNT reaches 6, the system will assert an output ALARM and the COUNT will not increase further, till it is reset by giving 0s at D_IN for 3 consecutive cycles. Write a VHDL program that implements such a system. Compile and verify the functionality of the program with appropriate test cases. 

 I am not really sure how to write this statement and code in VHDL if the current d_in is greater than the previous d_in by at least 2, a 3-bit output count is incremented.  I have written the entire code but i think it is wrong ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 20:42:19 11/05/2014 -- Design Name: -- Module Name: D2Q2Part2 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;   -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;   entity D2Q2Part2 is  Port ( D_IN : in STD_LOGIC_VECTOR (2 downto 0);  Clock: in STD_Logic;  Count : Buffer integer range 0 to 3;  Count2 : Buffer integer range 0 to 3;    Alarm : out STD_LOGIC); end D2Q2Part2;   architecture Behavioral of D2Q2Part2 is   begin   process(Clock) variable xnew,xold :STD_LOGIC_Vector (2 downto 0); begin   Count <= 0; Count2 <=2; if Clock'EVENT and Clock ='1' then  xnew:= D_IN;  xold:= xold + "010";   if D_IN = 0 then Count2 <= Count2 +1;  if D_In /= 0 then Count2 <= 0;  if Count2 =3 then Count <=0 ; Alarm <='0';      if xnew >= xold and count <7 then Count <= Count + 1;  if Count = 6 then Alarm <= '1';   end if; end if; end if; end if; end if; xold := xnew;   end if; end process;     end Behavioral;

[Altera_Forum]

a few problems here: 

 assigning count and count2 before the clock means that, in simulation, they will be assigned to 0/2 on every rising or falling edge of the clock unless overridden. So given your code, they may be assigned something on the rising edge, but on the falling edge they are reset back. This is probably different to the behaviour in real hardware as dual edge flip flops are illegal (it might throw an error in compilation)  I suggest you do not use variables as you are a beginner. Use only signals.  Your if tree does not match the requirement spec.  I suggest going back to a peice of paper and start by drawing out the circuit to do the specification. If you dont know the circuit, how do you expect to describe it? VHDL is a Hardware Description Language, not a programming language.