Verilog Coding

Intel® Quartus® Prime Software

Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Verilog Coding

1,105 Views

The following Verilog code is used to realize the SVPWM technique.The code has 5 modules.The module "sect_det" when run shows the output "sd" same for all clock cycles though it has inputs that vary with every clock cycle. I am unable to identify the bug.Please help me with the same. Also, the code needs to be optimized. Suggestions are welcomed.

Verilog Code is attached.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.