Verilog Synthesization

Altera_Forum · ‎02-04-2010

I could really use some help understanding how Quartus synthesizes. Below is a simple example that I believe will help me understand. I am trying to use the Vector Waveform to simulate what is happening. What I am trying to do it do is output Y1, Y2, Y3 every other time X is input (X is an 8-bit binary).

For the simulation I give X a random value every 10ns. The first time this happens I would expect Y1 to equal X, and Y2, Y3 to equal xxxxxxxx. Then the next time for Y2 to equal to first X that was input, Y1 to equal the new X, and Y3 to equal xxxxxxxx. I also expect these values to be output this time since it is every other (but this should not be relevant when looking at the values of Y1, Y2, Y3 in the waveform simulation and how they change over time).

But the problem is that Y1, Y2, Y3 all equal the input value of X with every new input. So every 10ns, the value of X, Y1, Y2, Y3 are all the same, equal to whatever X was set to input at.

I am sure there is something basic that I am not understanding, I really appreciate any help. Thanks.

module test(X, Y1, Y2, Y3);

input [7:0] X;

output [7:0] Y1, Y2, Y3;

reg [7:0] Y1, Y2, Y3;

reg ready = 1'b1;

always @(X) begin

Y3 = Y2;

Y2 = Y1;

Y1 = X;

if(ready)

ready = 0;

else

ready = 1;

if(ready)

/* Output Y1, Y2, and Y3 */

end

endmodule

Altera_Forum · ‎02-04-2010

To tell you the truth, I don't know what this will turn into. I see a bunch of latches. The whole module is asynchronous, I don't suppose by chance you're allowed to have a clock are you?

I'll take your word for it that it actually synthesizes. I'd love to see the warning message Quartus prints out when it does. Actually I'm going to try it and see what happens.

How about this: (assume X changes on the clock)

module test(
    input               clk,
    input          x, 
    output  reg    y1,
    output  reg    y2,
    output  reg    y3);
reg ready = 1'b1;
always @(posedge clk) begin
        ready   <= ~ready;
    if(ready) begin
        y3      <= y2;
        y2      <= y1;
        y1      <= x;
    end
endmodule

Altera_Forum · ‎02-04-2010

Thanks for the advice. At this point I am not sure if there will be a clock, so I was just assuming that there wouldn't and that it would change whenever the input changed. The warnings are below. The first 3 make sense because of the sensitivity list. And the others have to do with pin assignments which I haven't done yet. I just don't understand why Y1, Y2, Y3 change as they do? It does not make sense with my understanding of the logic behind and always block and blocking assignments...? Any ideas on how Quartas is working?

Warning (10235): Verilog HDL Always Construct warning at error_cancellation_filter.v(18): variable "D2" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10235): Verilog HDL Always Construct warning at error_cancellation_filter.v(19): variable "D1" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning (10235): Verilog HDL Always Construct warning at error_cancellation_filter.v(22): variable "ready" is read inside the Always Construct but isn't in the Always Construct's Event Control

Warning: No exact pin location assignment(s) for 32 pins of 32 total pins

Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

Warning: Found 24 output pins without output pin load capacitance assignment

Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.