Re: Very slow clock signals and STA in TimeQuest

Altera_Forum · ‎08-09-2012

For some specific usage, I need some very slow clock signals. They are generated from FPGA for outside chip.

For example, the FPGA clock is 40Mhz, so clock period is 25ns and I named this clock as clk_25ns. I need a clock signal which period is 6400ns or even slower, PLL inside FPGA may not generate so slow clock (it depends on the FPGA series)。 An approach I use is using a counter, like 8 bit counter, the input clock is clk_25ns, and the MSB in output, the period will approximately be 6400ns (25ns * 256).

I have two questions about this:

1. Using counter to generate a clock signal is not a good approach since it is not accurate and there may be large skew because it does not use global clock bus. Is there any other approach to create the slow clock signal instead of using counter?

2. For STA, the commands I always use in .sdc is:

create_clock -name sys_clk -period 25.0 [get_ports clk_25ns]

derive_pll_clocks

derive_clock_uncertainty

If I have to use counter to generate a clock signal, how can I program in my .sdc file to let TimeQuest know this is a clock signal? I just start to learn how to use TimeQuest.

Thanks very much.

Altera_Forum · ‎08-09-2012

You use the create_generated_clock command

create_generated_clock -name slow_clock -source sys_clock -divide_by 256 [get_registers slow_clock_register]

Altera_Forum · ‎08-09-2012

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You use the create_generated_clock command

create_generated_clock -name slow_clock -source sys_clock -divide_by 256 [get_registers slow_clock_register]

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Just be careful with this. The -clock option cannot actually take the name of a clock as an argument. You can use -clock [get_ports clk_25ns] instead. Also, since your counter is composed of multiple registers, make sure you specify the actual bit you want the clock tied to, e.g. [get_registers slow_clock_register[7]], or even more specific [get_pins slow_clock_register[7]|q].

Altera_Forum · ‎08-09-2012

Thanks very much, both of you. Do you have any suggestions about better approach to create slow clock signal instead of using counter?

Thanks again.

Altera_Forum · ‎08-09-2012

Using a counter is usually fine for such a slow clock, as long as you constrain it with the create_generated_clock constraint. The tools will typically drive it through a clock buffer (altclkctrl), or you can do it manually. Alternatively you could cascade plls, but you'll need to phase align it to the fast clock when you do transfers

Altera_Forum · ‎08-09-2012

I think you'll be okay with the counter. Just make sure it's a synchronous counter and not a ripple counter. As mentioned, if you're concerned about clock skew for nodes you are driving with this clock, you can put it on a Global buffer. If it has a lot of loads on it, the Fitter will likely auto-promote it to a Global anyway. If not, you can manually add it.

Altera_Forum · ‎08-09-2012

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Using a counter is usually fine for such a slow clock, as long as you constrain it with the create_generated_clock constraint. The tools will typically drive it through a clock buffer (altclkctrl), or you can do it manually. Alternatively you could cascade plls, but you'll need to phase align it to the fast clock when you do transfers

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I think you'll be okay with the counter. Just make sure it's a synchronous counter and not a ripple counter. As mentioned, if you're concerned about clock skew for nodes you are driving with this clock, you can put it on a Global buffer. If it has a lot of loads on it, the Fitter will likely auto-promote it to a Global anyway. If not, you can manually add it.

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Thanks a lot, both of you. Is the global buffer same as the clock buffer (altclkctrl)?

Thanks.

Altera_Forum · ‎08-09-2012

check out the clock network docs for your particular architecture. it will list what type of clock regions are available.

you get peripheral clocks (pclk), regional, dual-regional, and global (did I miss any?). I'm not sure by default what the tool will choose if you leave the altclkctrl as "AUTO", because it probably depends on the fanout.

Make sure you look at timing too. globals will help fanout in a large design, but you usually sacrifice time spent getting to and from the clock networks. I have had many designs have better results with regional or dual-regional clocks.

Altera_Forum · ‎08-09-2012

--- Quote Start ---

check out the clock network docs for your particular architecture. it will list what type of clock regions are available.

you get peripheral clocks (pclk), regional, dual-regional, and global (did I miss any?). I'm not sure by default what the tool will choose if you leave the altclkctrl as "AUTO", because it probably depends on the fanout.

Make sure you look at timing too. globals will help fanout in a large design, but you usually sacrifice time spent getting to and from the clock networks. I have had many designs have better results with regional or dual-regional clocks.

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Thanks. you mentioned "check out the clock network docs for your particular architecture", do you mean the doc from Altera for specific FPGA chip? For example, I use Cyclone IV E family FPGA, I should check the document for them, right?