Video rate dual port RAM filter question

[Altera_Forum]

Hello All, 

 A video rate FIR filter needs to be constructed, 31 taps x 12 bits. Also, NIOS needs to be able to update the coefficients on the fly.  Video will be sampled at clock rate, so all of the coefficients need parallel access.  The coefficient array is going to be symmetrical, so can be folded back to 16 elements(?).  Any better implementation suggestions other than making 16 x 12 bit individual dual-port RAM slices ?  Thanks,  Mark

[Altera_Forum]

--- Quote Start ---  Hello All,  A video rate FIR filter needs to be constructed, 31 taps x 12 bits. Also, NIOS needs to be able to update the coefficients on the fly.  Video will be sampled at clock rate, so all of the coefficients need parallel access.  The coefficient array is going to be symmetrical, so can be folded back to 16 elements(?).  Any better implementation suggestions other than making 16 x 12 bit individual dual-port RAM slices ?  Thanks,  Mark  --- Quote End ---    one option is using registers (16x12) if you can afford it. The other option is to concatenates sets of coefficients together so you use one address and split up the coeffs back.

[Altera_Forum]

Thank you for the suggestions. 

 Given that the video side is read only, and the NIOS is write only, the registers make a lot of sense (I had my head stuck with the idea of dual-port RAM). Also, the registers are likely to be much lower resource overhead than the associated DP RAM.  A dual port 192 x 1 packed array is scary, plenty of oppertunities to misplace a bit or two.  Regards, Mark