Re: Virtual JTAG counter to TDO

Altera_Forum · ‎03-31-2015

Hi everyone,

I'm new in FPGA verilog system. I have a DE0 nano from Terasic (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=593&from=fb-like).

During my little training (principally on the internet), I heard about the virtual JTAG. After searching examples and Altera documents, I create a project where I would like us the vJTAG.

I create a simple counter where I implement a virtual JTAG to see which value this counter have. My counter work correctly, and I can communicate with FPGA.

But I have a little problem and I can not resolve it.

When the value of my counter go to TDO, I read a read a wrong value (when I have 0000 0001, I have 0000 0010). I really don't understand. Maybe I do something wrong and miss something in the process of the vJTAG.

Here is my code :

Verilog code :


module vjiInterface(
    input  out_data,
    output reg  visual
    );
wire tck, tdi;
reg tdo;
wire  ir_in;
wire  ir_out;
wire v_cdr, v_sdr,v_udr,v_e1dr,v_pdr,v_e2dr,v_cir,v_uir;
reg  dr1_tmp_reg =0;
assign ir_out = ir_out;
reg cdr_delayed, sdr_delayed;
myVJI myVJI(
    .tdi(tdi),                
    .tdo(tdo),                
    .ir_in(ir_in),              
    .ir_out(ir_out),             
    .virtual_state_cdr(v_cdr),  
    .virtual_state_sdr(v_sdr),  
    .virtual_state_e1dr(v_e1dr), 
    .virtual_state_pdr(v_pdr),  
    .virtual_state_e2dr(v_e2dr), 
    .virtual_state_udr(v_udr),  
    .virtual_state_cir(v_cir),  
    .virtual_state_uir(v_uir),  
    .tck(tck)                 
    );
always @(negedge tck)
begin
    cdr_delayed = v_cdr;
   sdr_delayed = v_sdr;
end
always @(posedge tck)
begin
    case (ir_in)
        00 :
        begin
            if (cdr_delayed)
            begin
                dr1_tmp_reg = out_data;
                visual = dr1_tmp_reg;
            end
            else
            begin
                if(sdr_delayed)
                tdo = dr1_tmp_reg;
                dr1_tmp_reg = {dr1_tmp_reg,dr1_tmp_reg};
            end
        end
    endcase
end
endmodule

TCL code (part where I catch data from TDO)


proc recv {} {
    device_virtual_ir_shift -instance_index 0 -ir_value 0 -no_captured_ir_value
    set tdi 
        return $tdi
}

Visualization : Counter value : 0000 0011 / and after a TDO operation : 0000 0110

http://www.alteraforum.com/forum/attachment.php?attachmentid=10461&stc=1

Thanks for the help.

Sorry for my english's mistakes.

Hellikandra

Altera_Forum · ‎04-02-2015

Hi,

I do another test. And with a simple shift register Parallel in serial out, all work correctly.

I have changed a part of my code

I work every positive edge clock. But nothing change.


always @(posedge tck)
begin
	case (ir_in)
		00 :
		begin
			if (v_cdr)
			begin
				dr1_tmp_reg = out_data;
				visual = dr1_tmp_reg;
			end
			else
			begin
				if(v_sdr)
				tdo = dr1_tmp_reg;
				dr1_tmp_reg = {dr1_tmp_reg,dr1_tmp_reg};
			end
		end
	endcase
end

Is the TDO do a first one bit shift before sending information ?

Altera_Forum · ‎04-03-2015

This is the code easier :


module counterVjtag(
	// input
	input clock50,
	input key0, // reset for counter
	// output
	output  blinkLed
	);
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
assign blinkLed=  catchValue;
	
// counter reg & wire
wire clk001;
reg  bigCounter;
reg  catchValue;
myPLL myPLL(
	.inclk0(clock50),
	.c0(clk001) // clock @ 10kHz
	);
// virtual JTAG reg & wire
reg tdo;
wire ir_in,ir_out;
wire tck;
wire v_cdr,v_sdr;
reg  dr1_tmp_reg;
assign ir_out = ir_in;
myvirtualJTAG myvirtualJTAG(
		// input
		.tdo(tdo),
		.ir_out(ir_out),	// 
		// output
		.tdi(),
		.ir_in(ir_in),	// 
		.virtual_state_cdr(v_cdr), 
		.virtual_state_sdr(v_sdr), 
		.virtual_state_e1dr(),
		.virtual_state_pdr(), 
		.virtual_state_e2dr(),
		.virtual_state_udr(), 
		.virtual_state_cir(), 
		.virtual_state_uir(), 
		.tms(),               
		.jtag_state_tlr(),    
		.jtag_state_rti(),    
		.jtag_state_sdrs(),   
		.jtag_state_cdr(),    
		.jtag_state_sdr(),    
		.jtag_state_e1dr(),   
		.jtag_state_pdr(),    
		.jtag_state_e2dr(),   
		.jtag_state_udr(),    
		.jtag_state_sirs(),   
		.jtag_state_cir(),    
		.jtag_state_sir(),    
		.jtag_state_e1ir(),   
		.jtag_state_pir(),    
		.jtag_state_e2ir(),   
		.jtag_state_uir(),    
		.tck(tck)               
	);
always @(posedge clk001)
begin
	if (key0)
		begin
			bigCounter = bigCounter + 1;
			catchValue = bigCounter ;	
		end
	else
		bigCounter = 0;
end
always @(posedge tck)
begin
	case (ir_in)
		0 :
			begin
				if(v_cdr)
					dr1_tmp_reg = catchValue;
				else
					if(v_sdr)
						begin
							tdo = dr1_tmp_reg;
							dr1_tmp_reg = dr1_tmp_reg >> 1;
						end
			end
	endcase
end
endmodule

It's not look like this code (from "Virtual JTAG Megafunction (sld_virtual_jtag) but here we put a value in the counter.


module counter (clock, my_counter);
input clock;
output  my_counter;
reg  my_counter;
always @ (posedge clock)
 if (load && e1dr) // decode logic: used to load the counter my_counter
 my_counter <= tmp_reg;
 else
 my_counter <= my_counter + 1;
// Signals and registers declared for VJI instance
wire tck, tdi;
reg tdo;
wire cdr, eldr, e2dr, pdr, sdr, udr, uir, cir;
wire  ir_in;
// Instantiation of VJI
my_vji VJI_INST(
 .tdo (tdo),
 .tck (tck),
 .tdi (tdi),
 .tms(),
 .ir_in(ir_in),
 .ir_out(),
 .virtual_state_cdr (cdr),
 .virtual_state_e1dr(e1dr),
 .virtual_state_e2dr(e2dr),
 .virtual_state_pdr (pdr),
 .virtual_state_sdr (sdr),
 .virtual_state_udr (udr),
 .virtual_state_uir (uir),
 .virtual_state_cir (cir)
);
// Declaration of data register
reg  tmp_reg;
// Deocde Logic Block
// Making some decode logic from ir_in output port of VJI
wire load = ir_in && ~ir_in;
// Bypass used to maintain the scan chain continuity for
// tdi and tdo ports
bypass_reg <= tdi;
// Data Register Block
always @ (posedge tck)
 if ( load && sdr )
 tmp_reg <= {tdi, tmp_reg};
// tdo Logic Block
always @ (tmp_reg or bypass_reg)
 if(load)
 tdo <= tmp_reg
else
 tdo <= bypass_reg;
endmodule

Altera_Forum · ‎05-04-2015

Sorry to come back to you....

Someone have an idea ? I search again and again.

If I ceate an FIFO instance, Is it possible that resolve my problem ? And how can I implement that in my design ?

Thanks for helping

Altera_Forum · ‎07-28-2015

Try output to tdo with combinational design.

E.g.

assign tdo = (sdr_delayed)? dr1_tmp_reg[0] : 1'b0;

and shift the dr1_tmp_reg on tck rising edge as what you did in your code

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