Warning (14130) Reduced register with stuck

[Altera_Forum]

Hi, I try to simulate follow code, but when I simulate it, Quartus II says:

Warning (14130): Reduced register "PWM_Accumulator0[6]" to stuck with stuck data_in port to stuck value GND

I dont know why, but could it not simulate it... Please, I need your help!!!

VHDL code:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY altera_mf;

USE altera_mf.all;

ENTITY RAM IS

PORT

(

address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);

clock : IN STD_LOGIC ;

data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

wren : IN STD_LOGIC ;

q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

--------------------

start : in std_logic;

clockPWM : in std_logic;

reset : in std_logic;

enable : in std_logic;

PWM_out0 : out std_logic;

PWM_out1 : out std_logic;

motor1_dir : out std_logic;

motor1_esq : out std_logic;

motor2_dir : out std_logic;

motor2_esq : out std_logic;

--------------------

sensor1 : in std_logic;

sensor2 : in std_logic

);

END RAM;

ARCHITECTURE SYN OF ram IS

signal sub_wire0 : std_logic_vector (7 downto 0);

signal PWM_Accumulator0 : std_logic_vector(8 downto 0);

signal PWM_Accumulator1 : std_logic_vector(8 downto 0);

signal q0 : std_logic_vector(7 downto 0) := "00000000";

signal q1 : std_logic_vector(7 downto 0) := "00000000";

signal q2 : std_logic_vector(7 downto 0) := "00000000";

signal q3 : std_logic_vector(7 downto 0) := "00000000";

signal PWM_in0 : std_logic_vector(7 downto 0) := "00000000";

signal PWM_in1 : std_logic_vector(7 downto 0) := "00000000";

signal andclk0 : std_logic_vector(7 downto 0) := "00000000";

signal andclk1 : std_logic_vector(7 downto 0) := "00000000";

signal andclk2 : std_logic_vector(7 downto 0) := "00000000";

signal andclk3 : std_logic_vector(7 downto 0) := "00000000";

signal data_en0 : std_logic;

signal data_en1 : std_logic;

signal data_en2 : std_logic;

signal data_en3 : std_logic;

signal and0_1 : std_logic;

signal and0_2 : std_logic;

signal and1_1 : std_logic;

signal and1_2 : std_logic;

signal and2_1 : std_logic;

signal and2_2 : std_logic;

signal and3_1 : std_logic;

signal and3_2 : std_logic;

signal sensor_in1 : std_logic;

signal sensor_in2 : std_logic;

signal motor1_on : std_logic;

signal motor2_on : std_logic;

COMPONENT altsyncram

GENERIC (

clock_enable_input_a : STRING;

clock_enable_output_a : STRING;

intended_device_family : STRING;

lpm_hint : STRING;

lpm_type : STRING;

numwords_a : NATURAL;

operation_mode : STRING;

outdata_aclr_a : STRING;

outdata_reg_a : STRING;

power_up_uninitialized : STRING;

ram_block_type : STRING;

widthad_a : NATURAL;

width_a : NATURAL;

width_byteena_a : NATURAL

);

PORT (

wren_a : IN STD_LOGIC ;

clock0 : IN STD_LOGIC ;

address_a : IN STD_LOGIC_VECTOR (14 DOWNTO 0);

q_a : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

data_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0)

);

END COMPONENT;

BEGIN

q <= sub_wire0(7 DOWNTO 0);

altsyncram_component : altsyncram

GENERIC MAP (

clock_enable_input_a => "BYPASS",

clock_enable_output_a => "BYPASS",

intended_device_family => "Cyclone II",

lpm_hint => "ENABLE_RUNTIME_MOD=NO",

lpm_type => "altsyncram",

numwords_a => 32768,

operation_mode => "SINGLE_PORT",

outdata_aclr_a => "NONE",

outdata_reg_a => "UNREGISTERED",

power_up_uninitialized => "FALSE",

ram_block_type => "M4K",

widthad_a => 15,

width_a => 8,

width_byteena_a => 1

)

PORT MAP (

wren_a => wren,

clock0 => clock,

address_a => address,

data_a => data,

q_a => sub_wire0

);

process(enable, reset, address, wren, sub_wire0)

begin -- ||byte flags motores||

and0_1 <= not wren; -- habilitado para leitura 

and0_2 <= address(0) and not address(1) and not address(2); -- end "001"

data_en0 <= and0_1 and and0_2;

andclk0(0) <= data_en0 and sub_wire0(0);

andclk0(1) <= data_en0 and sub_wire0(1);

andclk0(2) <= data_en0 and sub_wire0(2);

andclk0(3) <= data_en0 and sub_wire0(3);

andclk0(4) <= data_en0 and sub_wire0(4);

andclk0(5) <= data_en0 and sub_wire0(5);

andclk0(6) <= data_en0 and sub_wire0(6);

andclk0(7) <= data_en0 and sub_wire0(7);

and1_1 <= not wren; -- ||byte flags sensores||

and1_2 <= not address(0) and address(1) and not address(2); -- end "010"

data_en1 <= and1_1 and and1_2;

andclk1(0) <= data_en1 and sub_wire0(0);

andclk1(1) <= data_en1 and sub_wire0(1);

andclk1(2) <= data_en1 and sub_wire0(2);

andclk1(3) <= data_en1 and sub_wire0(3);

andclk1(4) <= data_en1 and sub_wire0(4);

andclk1(5) <= data_en1 and sub_wire0(5);

andclk1(6) <= data_en1 and sub_wire0(6);

andclk1(7) <= data_en1 and sub_wire0(7);

and2_1 <= not wren; -- ||byte duty cycle motor1||

and2_2 <= not address(0) and address(1) and address(2); -- end "011"

data_en2 <= and2_1 and and2_2;

andclk2(0) <= data_en2 and sub_wire0(0);

andclk2(1) <= data_en2 and sub_wire0(1);

andclk2(2) <= data_en2 and sub_wire0(2);

andclk2(3) <= data_en2 and sub_wire0(3);

andclk2(4) <= data_en2 and sub_wire0(4);

andclk2(5) <= data_en2 and sub_wire0(5);

andclk2(6) <= data_en2 and sub_wire0(6);

andclk2(7) <= data_en2 and sub_wire0(7);

and3_1 <= not wren; -- ||byte duty cycle motor2||

and3_2 <= address(0) and not address(1) and not address(2); -- end "100"

data_en3 <= and3_1 and and3_2;

andclk3(0) <= data_en3 and sub_wire0(0);

andclk3(1) <= data_en3 and sub_wire0(1);

andclk3(2) <= data_en3 and sub_wire0(2);

andclk3(3) <= data_en3 and sub_wire0(3);

andclk3(4) <= data_en3 and sub_wire0(4);

andclk3(5) <= data_en3 and sub_wire0(5);

andclk3(6) <= data_en3 and sub_wire0(6);

andclk3(7) <= data_en3 and sub_wire0(7);

if reset='1' then

q0(0) <= '0';

q0(1) <= '0';

q0(2) <= '0';

q0(3) <= '0';

q0(4) <= '0';

q0(5) <= '0';

q0(6) <= '0';

q0(7) <= '0';

q1(0) <= '0';

q1(1) <= '0';

q1(2) <= '0';

q1(3) <= '0';

q1(4) <= '0';

q1(5) <= '0';

q1(6) <= '0';

q1(7) <= '0';

q2(0) <= '0';

q2(1) <= '0';

q2(2) <= '0';

q2(3) <= '0';

q2(4) <= '0';

q2(5) <= '0';

q2(6) <= '0';

q2(7) <= '0';

q3(0) <= '0';

q3(1) <= '0';

q3(2) <= '0';

q3(3) <= '0';

q3(4) <= '0';

q3(5) <= '0';

q3(6) <= '0';

q3(7) <= '0';

elsif enable'event and enable='1' then

q0(0) <= andclk0(0);

q0(1) <= andclk0(1);

q0(2) <= andclk0(2);

q0(3) <= andclk0(3);

q0(4) <= andclk0(4);

q0(5) <= andclk0(5);

q0(6) <= andclk0(6);

q0(7) <= andclk0(7);

q1(0) <= andclk1(0);

q1(1) <= andclk1(1);

q1(2) <= andclk1(2);

q1(3) <= andclk1(3);

q1(4) <= andclk1(4);

q1(5) <= andclk1(5);

q1(6) <= andclk1(6);

q1(7) <= andclk1(7);

q2(0) <= andclk2(0);

q2(1) <= andclk2(1);

q2(2) <= andclk2(2);

q2(3) <= andclk2(3);

q2(4) <= andclk2(4);

q2(5) <= andclk2(5);

q2(6) <= andclk2(6);

q2(7) <= andclk2(7);

q3(0) <= andclk3(0);

q3(1) <= andclk3(1);

q3(2) <= andclk3(2);

q3(3) <= andclk3(3);

q3(4) <= andclk3(4);

q3(5) <= andclk3(5);

q3(6) <= andclk3(6);

q3(7) <= andclk3(7);

end if;

PWM_in0(7) <= q2(7);

PWM_in1(7) <= q3(7);

end process;

process(clockPWM, PWM_in0, PWM_in1, sensor1, sensor2)

begin

if rising_edge(clockPWM) then 

PWM_Accumulator0 <= ("0" & PWM_Accumulator0(7 downto 0)) + ("0" & PWM_in0);

PWM_Accumulator1 <= ("0" & PWM_Accumulator1(7 downto 0)) + ("0" & PWM_in1);

end if;

end process;

motor1_on <= q0(0);

motor2_on <= q0(1);

motor1_dir <= q0(2);

motor1_esq <= not q0(2);

motor2_dir <= q0(3);

motor2_esq <= not q0(3);

sensor_in1 <= q1(0) and sensor1;

sensor_in2 <= q1(1) and sensor2;

PWM_out0 <= PWM_Accumulator0(8) and start and not sensor_in1 and motor1_on;

PWM_out1 <= PWM_Accumulator1(8) and start and not sensor_in2 and motor2_on;

END SYN;

[Altera_Forum]

--- Quote Start ---  "PWM_Accumulator0[6]" to stuck with stuck data_in port to stuck value GND  --- Quote End ---  The reason is in your arithmetic. Only PWM_in0(7) can be different from zero, thus PWM_Accumulator0(6 downto 0) are stuck to "000000". Please don't expect a comment, where the problem is located in your code.

[Altera_Forum]

alright, thank you