Warning: Timing-driven synthesis is skipped because there are multiple hierarchies in

[Altera_Forum]

When compiling my design i get the following warings. 

 Warning: Timing-driven synthesis is skipped because there are multiple hierarchies in the design Warning: Timing-driven synthesis is skipped because it could not initialize the timing netlist   I think this is the reason I am getting some timing issues with my design.   What does it mean and how do I fix it.   All help would be appreciated.

[Altera_Forum]

--- Quote Start ---  When compiling my design i get the following warings.   Warning: Timing-driven synthesis is skipped because there are multiple hierarchies in the design Warning: Timing-driven synthesis is skipped because it could not initialize the timing netlist   I think this is the reason I am getting some timing issues with my design.   What does it mean and how do I fix it.   All help would be appreciated.  --- Quote End ---    Hi,  looks strange. Are you using design partitions ? Is the SDC file in the project included? Which device are you using ?  Kind regards  GPK

[Altera_Forum]

Thanks for you reply. 

 I am using a stratixIII device. I dont think the project has any design partitions but it has 4 SDC files, to cover different parts of the design.

[Altera_Forum]

--- Quote Start ---  Thanks for you reply.   I am using a stratixIII device. I dont think the project has any design partitions but it has 4 SDC files, to cover different parts of the design.  --- Quote End ---    Hi,  I forgot there is a similar thread in the forum :   http://www.alteraforum.com/forum/showthread.php?t=6117  DrJohn issued a service request and got the answer that the problem could be caused by failing constraints in the SDC file. Have a look to the thread, maybe it helps. Otherwise I would recommend to issue a service request again.  Kind regards  GPK