What PLL ratios are legal

[Altera_Forum]

I would like to use a PLL to multiply a clock. I am using Stratix V, Quartus 16.1, have a 50MHz base clock, and would like to run my circuit e.g. at 107894736Hz. So I specified the following on the PLL: 

reference_clock_frequency "50.000000 MHz" number_of_clocks, 1 output_clock_frequency0, "107894736 Hz"  The reason I thought these settings might work is that 50000000 * 41 / 19 = 107894736.8. Furthermore, the PLL is within a reliable design that works fine when a round clock frequency is specified. Instead, I am told the following: Error: PLL Output Counter parameter 'output_clock_frequency' is set to an illegal value of '107.894736 MHz' on node '....'. File: c:/altera/16.1/quartus/libraries/megafunctions/altera_pll.v Line: 749  Info: "107870370 Hz" is a legal value  I note that 50MHz * 233 / 108 = 107870370.3. So an apparently legal ratio isn't nicer in any obvious way than what I used.   I wondered what I was doing wrong. In particular, I would like to know how to determine what clock frequencies are legal without asking Quartus. If the answer is RTFM, which FM should I be looking in, please?

[Altera_Forum]

Maybe this? 

 https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08292014_38.html

[Altera_Forum]

You can figure out legal PLL parameters if you understand the PLL structure and requirements for VCO frequency. The :19 divider is a prime, respectively the VCO has to run run either at 107 MHz or 19*107 MHz which is neither possible. An additional restriction is imposed by the minimal PFD input frequency of 5 MHz.

[Altera_Forum]

--- Quote Start ---  You can figure out legal PLL parameters if you understand the PLL structure and requirements for VCO frequency. The :19 divider is a prime, respectively the VCO has to run run either at 107 MHz or 19*107 MHz which is neither possible. An additional restriction is imposed by the minimal PFD input frequency of 5 MHz.  --- Quote End ---    Many thanks for your reply. In case helps someone else, the constraints that need to be satisfied when using Stratix V are on page 39 of this link https://www.altera.com/en_us/pdfs/literature/hb/stratix-v/stx5_53001.pdf . A diagram those constraints apply to is e.g. here https://www.altera.com/support/support-resources/operation-and-testing/pll-and-clock-management/pll-basics.html