What's the right way to start gate level simulation ?

[Altera_Forum]

I've some doubt using Quartus II version 10.1 with ModelSim-Altera SE 6.6c. When I select to start a gate level simulation from Quartus, it prompts me for the timing model to use for simulation, then ModelSim starts, all necessary libraries and vho file for the selected timing model are self loaded; at this point I right click on my main entity, selecting the Simulate item from contextual menu: simulation window layout is sef adpoted. Next step I do is to add signals and edit waveform needed for simulation, finally I click on Run-All button in Wave pan to start simulation. Using this way the result is equal to a RTL simulation. Looking on web and after many tries I discovered that if I select from ModelSim menu the item "Simulate -> Start Simulation", it prompt for the entity to simulate and sdo/sdf file too: using this way gate level simulation keeps track of gate delays. I can use this method every time but it isn't very confortable: why should I tell ModelSim (every time I start a simulation) which entity and delay file to use when Quartus already prompts me for the timing model to use ? Is it a bad Quartus configuration problem ?  

 Thank you in advance. Best Regards Simone Navari

[Altera_Forum]

I'm a newbie but I start gate-level (timing) simulation as follows: In Quartus, Assignments -> Settings -> Simulation. In the new window I call up ModelSim-Altera as the EDA tool and check the 'Run gate-level simulation automatically after compilation' box. I supply a test bench file and check the 'Compile test bench' radio button. The bit which used to stop me from getting gate-level timing simulations performed is behind the 'More EDA Netlist Writer Settings...' button. Here I have 'Generate third-party EDA tool command script for RTL functional simulation' turned OFF and 'Generate third-party EDA tool command script for gate-level simulation' turned ON (or vice versa if I just want to check functionality). After compilation ModelSim starts, loads all that is needed and a timing waveform appears showing clock-to-output delays of the order of 7ns. The device I always specify in my training exercises is the Cyclone II device in my DE2 development board. Hope this helps. Maybe you can help me. When I use Quartus II v10.1 - given that I have also downloaded and installed ModelSim-Altera 10.1 which is v6.6c - why is ModelSim-Altera 6.5e the version that it calls up in NativeLink?

[Altera_Forum]

I tried your procedure but I get no time simulation, only a functional simulation. After "start simulation" I select the "library cycloneii" and "design gate_work", is this correct?

[Altera_Forum]

(cdupaty) Are you working inside ModelSim using a pre-compiled VHDL design and test bench pair (previously compiled in Quartus II)? If you are then I cannot help you because I have had problems using Modelsim as a standalone program, specifically, getting the device libraries loaded in. My previous suggestion was using Quartus II and starting ModelSim-Altera using the Nativelink feature. It is a little easier than I thought/suggested. You don't have to worry about anything behind the 'More EDA Netlist Writer Settings...' button. Just have the 'Run gate-level simulation automatically after compilation' checked. I tried stripping a design file and its test bench file out of a simple project, deleting the project and starting again loading the two files into Quartus and compiling. ModelSim-Altera starts, my test bench script runs and timing delays are present. Inside ModelSim-Altera, in the transcript window I can enter 'Restart' to clear the current simulation (and OK the list of stuff that comes up) and enter 'Run 4 us' or whatever and it resimulates with timing delays. What I can't do is go 'Restart' to clear the current simulation and then go Simulation -> Start Simulation. Sure enough the design and test bench and device libraries are in there (under the different tabs) but it fails. Why? Because it cannot find an instance of my design file (DUT but it could be called anything) in the mydesign_vhd.sdo file. Rightly so because it's not there. I think to use ModelSim in this way you will have to start a project in ModelSim (PE student edition) and compile your files there. But the fun starts when you want to get the device library loaded and I haven't worked out how to do that yet. Perhaps there is a ModelSim guru reading who could help us all.

[Altera_Forum]

Thanks for your help...  

I'm looking for the guru and post the good procedure. Have a nice new year  C.Dupaty Aix en Provence France