Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Whether the latches in design power-up with a default value 0 ?


According to Quartus Handbook on Topic Power-Up Level - "Registers in the device core hardware power up to 0 in all Altera devices." Do Latches also implemented with same behavior? If so how to enable them. Current default does not seem to have this power-up value.


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Valued Contributor III

Physical registers power up to logic zero in the devices, but you can get a register to effectively power up to a logic one by inserting the sense of the logic (and Quartus can do that for you automatically). Thus the declarations (in verilog) 'reg somereg = 0;' and 'reg someother = 1;' are both legal and the registers will effectively power up to 0/1 respectively.


Latches are built with logic, so they will default to the value you have them assume (ie, can be 0 or 1 or 0/1 (ie, unknown)) depending on how you code the latch.

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