Hold time slack is minus, so how to solve this problem? How can I meet Timing requirements. Some specific files about my project are attached. Please download and help me analyze it and hope for your solutions. Thanks very much!
“FPGA_CLOCK_25MHZ” is the 25MHZ input clock， “pll_clk_out_50 ” is clock generated by PLL IP which is 50MHz, and “pll_clk_out_50 ” didn't meet the Timing analysis.
Open Timing Analyzer, update timing netlist, and there will be a list of timing violations. Right click on the violated clock and click ‘Report Timing’. Export out these violated paths.