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KWang97
Beginner
237 Views

Timing Analysis not met on holdtime

Hold time slack is minus, so how to solve this problem? How can I meet Timing requirements. Some specific files about my project are attached. Please download and help me analyze it and hope for your solutions. Thanks very much!

 

“FPGA_CLOCK_25MHZ” is the 25MHZ input clock, “pll_clk_out_50 ” is clock generated by PLL IP which is 50MHz, and “pll_clk_out_50 ” didn't meet the Timing analysis.

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3 Replies
skyjuice
Employee
83 Views

Can you do a report_timing on the violated path? This will pinpoint to what cause the hold violations.

KWang97
Beginner
83 Views

Hi How do a report_timing on the violated path? I don’t know how to get it, could you please show me specific steps on how to generate it. Thanks!
skyjuice
Employee
83 Views

Open Timing Analyzer, update timing netlist, and there will be a list of timing violations. Right click on the violated clock and click ‘Report Timing’. Export out these violated paths.

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