Hi, I am using Quartus Prime Standard 17.0.2 for Windows. The altera_reserved_tck is constrained in the .sdc file, but the FMAX in the Timequest View Report does not show the altera_reserved_tck. Is this a new bug for the Quartus 17.0.2? Or anyway to simply show the FMAX of the altera_reserved_tck in the Timequest? Thanks.
altera_reserved_tck is the JTAG clock. For some reason, in recent versions of the software, you have to constrain otherwise it shows up as an unconstrained clock (not that the constraint really does much since it's all fixed hardware). There's no real need to see an fmax for this.
The altera_reserved_tck is already constrained in the .sdc file. In an earlier question related to partial reconfiguration, I was helped by Intel support to lower JTAG clock frequency to make partial reconfiguration thru JTAG work. So I believe that FMAX should include the altera_reserved_tck frequency. As helped in that PR related question, the JTAG path may be synthesized. The possibility exists that the JTAG path may not meet the constraints in the .sdc. I don't remember whether earlier version of Quartus included altera_reserved_tck in the FMAX. If it did, then the 17.0.2 has a bug. If not, suggest Intel to include it in newer version. Even if JTAG path was fixed in placement, the TDI, TDO, TMS timing constraints related to TCK but coming from board may cause violation, depending on how the constraints are written, and in that sense, the FMAX should still include the altera_reserved_tck. Thanks.