Why does Qsys create copies of the source files when it generates a system?

[gyuunyuu]

When we "generate" a Qsys system for synthesis (as well as for simulation), Qsys fills in the synthesis and simulation files inside Qsys system folder. Here, it creates copies of RTL files that must exist elsewhere in the project directory. Also, via a tcl script which exists inside the synthesis folder, all these files are assigned to a library which has same name as the Qsys system itself.

We have adopted tools to automate the process of compiling the files and running simulation. The above results in us having duplicate files that exist in two libraries.  One is our own custom library to store certain RTL files while the other is one created by Qsys.

One problem that results from all this is , during development, as we change the RTL files for custom Qsys components, we need to regenerate the system so the changes are copied into the Qsys synthesis files.

I have now following questions:

1. Why does Qsys create copy of RTL files and not just "link" to them?​
2. Is there a way to assign files inside Qsys system to specific libraries (from VHDL perspective) as we can do so in Quartus.

[Kenny_Tan]

1) The reason is Qsys want to make sure that user regenerate the IP, so that any changes to the qsys will reflect the error there rather than have it in the quartus synthesis

2) nope, the qsys will pick the libraries base on the files being generated. You can refer to hw.tcl files if you can pick a different libraries but i doubt so.

[Kenny_Tan]

any update?

[gyuunyuu]

Could you kindly elaborate the first point?

As for the second one , it seems that there is workaround for it, however it would be great if we can specify the library name for the Qsys system (rather than it being same as the Qsys system name itself) and also what libraries the source files for Qsys components should be added into. There is .tcl script in the form of .qip file but this gets overwritten each time we generate the system.

[Kenny_Tan]

I will get back to you on this.

[Kenny_Tan]

Here is the more explanation:

let me know if my understanding is not correct. You have your own set of custom RTL which they created _hw.tcl files (QSYS IP) for them to be used within Qsys. They then use Qsys to stitch them together and generate RTL for synthesis/simulation.

The reason why Qsys makes copies is because ultimately, these are "instances" or "variants" of the QSYS IP (_hw.tcl file). The Qsys Infrastructure is designed for this use case to have the capability to define different parameterization for the end-user. we assume your IPs are static RTL; but this was designed for variable RTL that is determined during run-time and such creates RTL for each variant. This is the reason why there seems to be duplicate copies.

[gyuunyuu]

​Yes, your understanding is correct.

When you say variants, is it that the HDL code itself is being changed or, is it that just the generic values being passed in (parameter in Verilog) are being changed by Qsys?

[Kenny_Tan]

It is the generic values being passed in (parameter in Verilog) are being changed by Qsys.