Why does TimeQuest show data arriving after the latch edge?

[okhajut]

Here is the waveform from Quartus Prime TimeQuest:

I know that the design meets timing since the fmax is more than 100MHz which is the target clock. So this question is specifically about why the waveform looks wrong. The waveform shows that the data arrival and data required are after the latch edge. Both of these are supposed to be before the latch edge isn't it?

[RichardTanSY_Altera]

It’s not necessary for both the DAT and DRT to occur before the latch edge.

Essentially, we focus on the setup/hold slack, which depends on the both the Data Arrival Path (DAT) and the Data Required Path (DRT). For setup, the DAT must be > DRT. For Hold, DRT > DAT.

For further details, you can check out this YouTube video:

https://www.youtube.com/watch?v=6D-w8mOttnE

We also have a video series on Timing Analyzer.

https://learning.intel.com/developer/learn/learning-plans/244/timing-analysis-with-the-intelr-quartusr-prime-pro-software

Additionally, TimeQuest User Guide:

https://web02.gonzaga.edu/faculty/talarico/CP430/LEC/TimeQuest_User_Guide.pdf

Regards,

Richard Tan

[sstrell]

To further clarify, the launch and latch edges shown in the waveform view are when the clock source initiates those edges, not when they arrive at the register/logic being clocked.  So you can see the Data Required Time, represented by the dashed line as 3.467 ns after the clock source initiated the latch edge.  As such (and as mentioned above) everything is based on the data required time, not when the clock source initiated the clock pulse.  As long as the data arrives early enough before that time (launch edge + 3.467 ns) to meet the setup timing requirement of the logic, the path will meet timing.

[RichardTanSY_Altera]

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