Will Quartus support generic types?

[Altera_Forum]

Hi there, 

 I wonder if anyone has an idea how to achieve Generic Types, i.e., something like:    package fifo_pkg is generic (type element_type); type fifo_in_type is record data_in : element_type; rd : std_logic; wr : std_logic; end record; type fifo_out_type is record data_out : element_type; empty : std_logic; full : std_logic; end record; component fifo is generic ( MIN_DEPTH : integer; DATA_WIDTH : integer ); port ( clk : in std_logic; res_n : in std_logic; i : in fifo_in_type; o : out fifo_out_type ); end component fifo; end fifo_pkg;  so that one can use smth like:   package wide_fifo_pkg is new fifo_pkg generic map (type => std_logic_vector(31 downto 0)); with the current version of quartus?  Version 11.0sp1 of Quartus does not allow to synthesize the code above. I wonder if there are other ways to achieve the same flexibility with today's synthesis/vhdl 2008 support of quartus. Does anyone have a nice suggestion here?  Does anyone know if that will be possible with the upcoming version of quartus?  Thanks a million, T (ps: this is somehow a cross-posting of: http://stackoverflow.com/questions/7925361/passing-generics-to-record-port-types, i posted here because i guess that the community here will be more quartus-focused, and might have a clue when this will be integrated in quartus) 

[Altera_Forum]

In the present case, the intended feature can be easily achieved by using generics for the std_logic_vector width. In so far I didn't see the purpose of using generic types in your example. Do have any requirements beyond specifying the signal size?

[Altera_Forum]

Hi, 

 Thanks for the quick reply. You're right, one can use generics to define the width of the std_logic_vector type. But it get's tricky if you want to use records to group signals of your port specification, for example, look at the code again:  library ieee; use ieee.std_logic_1164.all; use work.math_pkg.all; package fifo_pkg is type fifo_in_type is record data_in : std_logic_vector(DATA_WIDTH_??- 1 downto 0); rd : std_logic; wr : std_logic; end record; type fifo_out_type is record data_out : std_logic_vector(DATA_WIDTH_?? - 1 downto 0); empty : std_logic; full : std_logic; end record; component fifo is generic ( MIN_DEPTH : integer; DATA_WIDTH : integer ); port ( clk : in std_logic; res_n : in std_logic; i : in fifo_in_type; o : out fifo_out_type ); end component fifo; end fifo_pkg;   As far as i understood, there is no way to use generics in records in Quartus. So that i could link DATA_WIDTH_?? to DATA_WIDTH from the component declaration. But i could do this with the code i posted in the previous post, so i could instantiate fifos of various width and depth's, and could use records to group the signals.  Sry for not being precise enough when posting this first...  Thanks, T

[Altera_Forum]

Yes, that apparently doesn't work with recent Quartus versions. There's still an option to specify a std_logic_vector of maximum size, but not to use all bits. The unused bits will be ignored in synthesis, but you possibly get some warnings. I'm doing similar by using not fully populated arrays.

[Altera_Forum]

2008 support is little more than the minor bits atm. I've been told full fixed package support is due in 12.1 so I'm hoping this covers the more complex parts like package genetics and generic types too.  

 atm, DATA_WIDTH will have to be a constant in a package. to be honest, if this is a generic that is the same for many entities it should be in a package anyway.

[Altera_Forum]

--- Quote Start ---  Yes, that apparently doesn't work with recent Quartus versions. There's still an option to specify a std_logic_vector of maximum size, but not to use all bits. The unused bits will be ignored in synthesis, but you possibly get some warnings. I'm doing similar by using not fully populated arrays.  --- Quote End ---    Thanks, i was thinking of something like that before. This seems to be somehow a quck'n'dirty hack. I wonder how this works if you connect ports in a top level entity. For example if you have the fifo, and then you connect it to a 8 bit data bus, when the fifo's max length is 32 bit. This won't compile, right? Do yo have an example for that?

[Altera_Forum]

--- Quote Start ---  2008 support is little more than the minor bits atm. I've been told full fixed package support is due in 12.1 so I'm hoping this covers the more complex parts like package genetics and generic types too.   --- Quote End ---   Any idea when 12.1 will be released? I'm new to quartus, so i don't know their release cycles yet..    --- Quote Start ---   atm, DATA_WIDTH will have to be a constant in a package. to be honest, if this is a generic that is the same for many entities it should be in a package anyway.  --- Quote End ---   Yes you are basically right, but in a design where you need several fifo's with different data_width's then the package generics would make sense.

[Altera_Forum]

--- Quote Start ---  Any idea when 12.1 will be released? I'm new to quartus, so i don't know their release cycles yet..   --- Quote End ---    no idea. we're on 11 sp1 now, and I guess 11.1 and 12.0 will be released first. so don't expect anything anytime soon. best to raise an issue on mysupport asking them this question.    --- Quote Start ---   Yes you are basically right, but in a design where you need several fifo's with different data_width's then the package generics would make sense.  --- Quote End ---    yes that is true. but one of the parts of vhdl 2008 that quartus does support now is unconstrained arrays and records. so you can declare records like this:   type my_record_t is record a : std_logic_vector; b : unsigned; --etc end record ...... signal a : my_record_t( a( N-1 downto 0), b( X-1 downto 0), ... );   so you declare the type in a package and use generics to set the sizes on a per entity basis.

[Altera_Forum]

--- Quote Start ---  no idea. we're on 11 sp1 now, and I guess 11.1 and 12.0 will be released first. so don't expect anything anytime soon. best to raise an issue on mysupport asking them this question.  yes that is true. but one of the parts of vhdl 2008 that quartus does support now is unconstrained arrays and records. so you can declare records like this:   type my_record_t is record a : std_logic_vector; b : unsigned; --etc end record ...... signal a : my_record_t( a( N-1 downto 0), b( X-1 downto 0), ... ); so you declare the type in a package and use generics to set the sizes on a per entity basis.  --- Quote End ---    Thanks. I did try that just now, however quartus fails (record element cannot have an unconstrained array type) on the record definition:   type my_record_t is record a : std_logic_vector; end record; I did put the following compiler directive in the file to let quartus know it's VHDL 2008:  --synthesis VHDL_INPUT_VERSION VHDL_2008 That should be ok, right?  Any hints on that, do you have a short example that compiles?  Thanks, T

[Altera_Forum]

sorry. don't have one now, but I've compiled a design with unconstrained arrays. not sure about that synthesis directive. but there is a compile option in the project settings menu to select vhdl2008 as the input language.

[Altera_Forum]

--- Quote Start ---  sorry. don't have one now, but I've compiled a design with unconstrained arrays. not sure about that synthesis directive. but there is a compile option in the project settings menu to select vhdl2008 as the input language.  --- Quote End ---    maybe quartus can handle unconstraint arrays but not unconstraint types in records.   I did find a similar post on edaboard: http://www.edaboard.com/thread224912.html#post959333 Seems that they came to the same conclusion....