Writing a host application that does not need to reprogram the FPGA

[Altera_Forum]

Hello community, 

 I am working on a project that requires the ability to run a host application on an OpenCL Kernel without programming the device during the execution of the host application. In other words, I would like to program the device once using:   aocl program acl0 vector_add.aocx  And then I would like to run the associate host program multiple times without it reprogramming the device as seen below:   Initializing OpenCL Platform: Intel(R) FPGA SDK for OpenCL(TM) Using 1 device(s) de5net_a7 : Terasic's Preferred Board Using AOCX: vector_add.aocx Reprogramming device with handle 1   It is my understanding that clcreateprogramwithbinary(...) is the OpenCL API call that programs the device. But I am wondering if there is any way around this? Can I create a program without reprogramming the device if it is already ready programmed with the target image? If I don't make this API call, I get "CL_INVALID_PROGRAM" later on in the execution of the host application.  This example uses the vector_add OpenCL design from Intel.  I know that "aocl diagnose acl0" is able to write to / read from global memory (DDR on the FPGA board) without reprogramming the device, but that does not exercise the kernel.  Thanks ahead of time. I am new to OpenCL, but I am very impressed with what this tool can do.

[Altera_Forum]

You can use "export CL_CONTEXT_COMPILER_MODE_ALTERA=3" to disable run-time reconfiguration. I regularly use this when benchmarking to prevent the FPGA from being reprogrammed every time. Just be careful that if you need to use run-time reconfiguration again, you must unset that environmental variable. It has happened to me multiple times that I forgot to unset it and a few days later tried to run a new kernel on the FPGA and was scratching my head for half an hour trying to figure out why I get "CL_INVALID_KERNEL_ARGS". :D

[Altera_Forum]

HRZ, thank you! I have been looking for this solution for about a month now... Doing what you mentioned worked perfectly. I am working with Quartus Prime 18.0 and a polite WARNING came up saying "CL_CONTEXT_COMPILER_MODE_ALTERA" is deprecated, please use "CL_CONTEXT_COMPILER_MODE_INTELFPGA". Either way it worked, but using the new variable name removed the warning. 

 Also for future readers, thanks to HRZ, I finally ran into this: https://www.altera.com/documentation/ewa1404851957878.html#ewa1405368788074 . It is the troubleshooting section of the Stratix V OpenCL porting guide. It lists environment variables and their functionality including this environment variable. From that page:  CL_CONTEXT_COMPILER_MODE_INTELFPGA  Unset this variable or set it to a value of 3. The OpenCL™ host runtime reprograms the FPGA as needed, which it does at least once during initialization. To prevent the host application from programming the FPGA, set this variable to a value of 3.  Important: When setting CL_CONTEXT_COMPILER_MODE_INTELFPGA, only use a value of 3.  Life saver. Thanks again.

[Altera_Forum]

Oh, yes, I am still using the "pre-Intel" versions of the compiler. :D

[forto1]

I am using the Cyclone V - DE10 nano Kit with FPGA SDK 16.1.

Where I set CL_CONTEXT_COMPILER_MODE_INTELFPGA=3? Is it possible?

[HRZ]

Since you are using a pre-Intel version of the compiler, just run "export CL_CONTEXT_COMPILER_MODE_ALTERA=3" from command line. Note that you must configure the FPGA manually using "aocl program" first.

When you are done, you should run "unset CL_CONTEXT_COMPILER_MODE_ALTERA" from command line if you want to go back to the default method of run-time reconfiguration by the host code.

[forto1]

In my main program I run a kernel many times inside a loop and then I need to reprogram other kernels because all the logic doesn't fit inside a single kernel. 

There is a command in c to export this variable within my main.c program and return this variable to normal after the for command? Thanks

[HRZ]

Then I don't think you need to use that environmental variable at all. By default, the FPGA will be reconfigured only once when you call clBuildProgram() (or maybe clCreateProgramWithBinary(), I don't remember exactly). After that, the FPGA will not be reconfigured again no matter how many times you call the kernel using clEnqueueNDRangeKernel() or clEnqueueTask(). When you want to switch to the second bitstream, you are going to have to call clBuildProgram() again which will reconfigure the FPGA again.