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Hi,
I have a project using a Qsys design targeting Stratix V. I'm using altera_temp_sense to get the core temperature. This works well in synthesis, but when I create a testbench for the design using Qsys it seems like the output file for the simulation model is nonsensical:
// (C) 2001-2019 Intel Corporation. All rights reserved.
[...]
// agreement for further details.
`timescale 1 ns / 1 ns
module altera_temp_sense (
corectl,
eoc,
reset,
tempout);
parameter DEVICE_FAMILY = "Arria 10";
input corectl;
input reset;
output eoc;
output [9:0] tempout;
assign eoc = 1'b0;
assign tempout = 10'h0;
endmodule
Surely this is incorrect? Looking into intelFPGA/19.1/ip/altera/altera_temp_sense/ I cannot see anything obvious I'm doing wrong either, it seems to simply lack a model.
ModelSim complains as well when executing the generated design script:
# ** Error (suppressible): testbench/[..].v(826): (vopt-2912) Port 'clk' not found in module 'altera_temp_sense' (1st connection).
# ** Error (suppressible): testbench/[..].v(826): (vopt-2912) Port 'tsdcalo' not found in module 'altera_temp_sense' (2nd connection).
# ** Error (suppressible): testbench/[..].v(826): (vopt-2912) Port 'tsdcaldone' not found in module 'altera_temp_sense' (3rd connection).
# ** Error (suppressible): testbench/[..].v(826): (vopt-2912) Port 'clr' not found in module 'altera_temp_sense' (4th connection).
Thanks,
EDIT: I double-checked the manual for the IP core and sure enough it says "Note: The Intel FPGA Temperature Sensor IP core does not have simulation model files and
cannot be simulated.". That's... annoying and quite unexpected.
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