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Altera_Forum
Honored Contributor I
1,184 Views

aoc compile error: using host channel feature

Hi,  

 

I am writing a simple OpenCL code for testing host channel feature introduced 17.1. 

The code is as follows: 

# pragma OPENCL EXTENSION cl_intel_fpga_host_pipe : enable kernel void clkernel( __attribute__((intel_host_accessible)) __read_only pipe ulong4 cl_input, __attribute__((intel_host_accessible)) __write_only pipe ulong4 cl_output) { ulong4 val; while( 1 ) { if( read_pipe(cl_input, &val)) { while( !write_pipe(cl_output, &val) ) ; } } }  

 

when compiling the code by aoc, error message was printed like this. 

$ which aoc 

/cad/intelFPGA/17.1/hld/bin/aoc 

$ aoc clkernel.cl 

aoc: Running OpenCL parser.... 

clkernel.cl:1:26: warning: unknown OpenCL extension 'cl_intel_fpga_host_pipe' - ignoring# pragma OPENCL EXTENSION cl_intel_fpga_host_pipe : enable 

1 warning generated. 

aoc: Optimizing and doing static analysis of code... 

Error: Channel has no point connection: ID= host_to_dev 

avm_channel_id_host_to_dev_read connection missing, or optimized away 

Error: Could not write system script to file. System generation aborted! 

Error: System integrator FAILED. 

Refer to clkernel/clkernel.log for details. 

 

 

 

 

What should I do next?
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5 Replies
Altera_Forum
Honored Contributor I
187 Views

I did a test and this doesn't work for me either. Probably some bug in the tool chain. I recommend opening a support ticket directly with altera.

Altera_Forum
Honored Contributor I
187 Views

HRZ, 

 

Thank you for you advise. 

I will open a ticket to report this situation. 

 

Best Regards,
Altera_Forum
Honored Contributor I
187 Views

Hi, 

 

May I know are you using the dedicated BSP(a10gx_hostch) for this feature compilation? 

 

Board list: 

a10gx 

Board Package: C:\intelFPGA_pro\17.1\hld\board\a10_ref 

 

a10gx_hostch 

Board Package: C:\intelFPGA_pro\17.1\hld\board\a10_ref 

Channels: host_to_dev, dev_to_host 

 

 

Regards, 

CloseCL 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
187 Views

 

--- Quote Start ---  

Hi, 

 

May I know are you using the dedicated BSP(a10gx_hostch) for this feature compilation? 

 

Board list: 

a10gx 

Board Package: C:\intelFPGA_pro\17.1\hld\board\a10_ref 

 

a10gx_hostch 

Board Package: C:\intelFPGA_pro\17.1\hld\board\a10_ref 

Channels: host_to_dev, dev_to_host 

 

 

Regards, 

CloseCL 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

The target BSP does not make any difference here since the compiler ignores the host channel extension all together because it is unknown to it. Either the name of the extension is something other than what is written in Altera's documents, or support for the extension is broken.
Altera_Forum
Honored Contributor I
187 Views

 

--- Quote Start ---  

Hi, 

 

May I know are you using the dedicated BSP(a10gx_hostch) for this feature compilation? 

 

Board list: 

a10gx 

Board Package: C:\intelFPGA_pro\17.1\hld\board\a10_ref 

 

a10gx_hostch 

Board Package: C:\intelFPGA_pro\17.1\hld\board\a10_ref 

Channels: host_to_dev, dev_to_host 

 

 

Regards, 

CloseCL 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

Thank you for your advice. 

There are no errors when using the BSP 'a10gx_hostch', 

but the warning described below are remained. 

clkernel.cl:1:26: warning: unknown OpenCL extension 'cl_intel_fpga_host_pipe' - ignoring 

 

Anyway, the compilation of the design is finished successfully.
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