array problem

[Altera_Forum]

Hello I'm trying to migrate from quartus 5.1 to 9.0 sp2. The problem I have is that 9.0 generates much more elements (11,000 instead of 5,000) than 5.1. And it all happens because of this code. 

  usb_data : PROCESS(ds) is  TYPE RAM is array (0 to 255) of unsigned(15 downto 0);  variable config :RAM;   variable ram_index :integer range 0 to 255; -- index into RAM array   BEGIN  if(ds'EVENT AND ds ='1') then  if(usb_rnw = '1') then -- read from RAM output to USB  ram_index := loc_addr;  usb_dout <= config(ram_index);  else -- in from USB write to RAM  ram_index := loc_addr;  config(ram_index) := usb_din;  end if;  end if; -- main ds event  end process usb_data;    I guess it is something to do with arrays. Has anyone any experience with this issue?

[Altera_Forum]

Nope 

But I would recommend making the ram a signal rather than a variable to follow the altera coding guidlines properly.

[Altera_Forum]

Are you targeting the same device? E.g. if you used an ACEX device and now changed it for a Cyclone IV, Quartus may not be able to infer the RAM-block and thus generates the 4096 registers and the necessary multiplexers. EAB Ram in ACEX could be accessed without registering in- or outputs. In your code the address is unregistered which is not available in Cyclone (and Stratix) memory blocks.

[Altera_Forum]

Yes I'm targeting the same device.

[Altera_Forum]

I chaged from variable declaration to signal. Still the same problem.

[Altera_Forum]

I added the missing definitions for a full design, and it infers internal RAM with Cyclone III and default synthesis settings in Quartus V9.0. 

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity test1 is port ( ds : in std_logic; loc_addr : in integer range 0 to 255; usb_rnw : in std_logic; usb_din : in unsigned(15 downto 0); usb_dout : out unsigned(15 downto 0) ); end entity; architecture rtl of test1 is begin usb_data : PROCESS(ds) is TYPE RAM is array (0 to 255) of unsigned(15 downto 0); variable config :RAM; variable ram_index :integer range 0 to 255; -- index into RAM array BEGIN if(ds'EVENT AND ds ='1') then if(usb_rnw = '1') then -- read from RAM output to USB ram_index := loc_addr; usb_dout <= config(ram_index); else -- in from USB write to RAM ram_index := loc_addr; config(ram_index) := usb_din; end if; end if; -- main ds event end process usb_data; end;