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Hi,
I have a design with two clocks. The first one (named "clk") is correctly assigned in my sdc file with:create_clock -name "clk" -period 5.000ns
but my second clock (named "clock2") is generating a warning. I've tried to add: create_clock -name "clock2" -period 40.000ns
but I still have a warning. "clock2" is not a port, it's generated from "clk". How should I assign that? Thank you.
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You need to use 'create_generated_clock'.
See quartus help on create_generated_clock (http://quartushelp.altera.com/15.0/mergedprojects/tafs/tafs/tcl_pkg_sdc_ver_1.5_cmd_create_generated_clock.htm). Cheers, Alex- Mark as New
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create_generated_clock -source [get_ports {clk}] <relationship to source> <target>
What structure in your design is creating clock2? If it's a PLL, you can use derive_pll_clocks to automatically create the generated clock. If not, you have to use create_generated_clock.- Mark as New
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Thank you both but I still have another warning:
Warning (332060): Node: *|clock2 was determined to be a clock but was found without an associated clock assignment.
Warning (332061): Virtual clock clock2 is never referenced in any input or output delay assignment.
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Hi,
--- Quote Start --- Warning (332060): Node: *|clock2 was determined to be a clock but was found without an associated clock assignment. --- Quote End --- Is related to the timing constrains not satisfied. --- Quote Start --- Warning (332061): Virtual clock clock2 is never referenced in any input or output delay assignment. --- Quote End --- Check that the virtual clock is not originally intended as non-virtual clock and specify the clock targets. Already addressed in previous thread. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)- Mark as New
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A virtual clock is created if you use create_clock and then don't set a target (an input clock port). It's used with set_input_delay or set_output_delay as the reference clock that drives the "upstream" or "downstream" device to/from the FPGA.
Post your updated sdc code.- Mark as New
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Thank you both.
Please tell me exactly what I have to do. Here is my sdc code:#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.1.0 Build 162 10/23/2013 SJ Full Version
#
# ************************************************************
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Clock constraints
create_clock -name "clk" -period 5.000ns
create_generated_clock -divide_by 8 -name clock2 -source
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
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The two warnings (note they are not errors) are directly related. You're creating a virtual clock but then not referencing it with any input or output port delay setting - set_input_delay or set_output_delay as sstrell suggested.
Please note: it does not mean the timing constraint has not been satisfied, as suggested elsewhere in the thread. Post your updated constraints. Cheers, Alex- Mark as New
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My sdc constraints are waiting for a moderator to agree...
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--- Quote Start --- create_generated_clock -source [get_ports {clk}] <relationship to source> <target> What structure in your design is creating clock2? If it's a PLL, you can use derive_pll_clocks to automatically create the generated clock. If not, you have to use create_generated_clock. --- Quote End --- You need to answer this question before people can really help you. PLL? Did you try "derive_pll_clocks"? If the answer is yes to both these questions then you don't need the sdc constraints t for clock 2 at all (it is generated by "derive_pll_clocks") Obviously you don't have a 200MHz and 25MHz clock coming directly from the same clock pin?
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You have not specified a target for your create_generated_clock constraint. That's why it's coming up as a virtual clock. If you are using a PLL, the target should be the output clock pin (get_pins) of the PLL, or just use derive_pll_clocks as mentioned.
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I don't use a PLL or input/output pins as it's a simple internal clock divider. I really don't know how to resolve these warnings.
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--- Quote Start --- I don't use a PLL or input/output pins as it's a simple internal clock divider. I really don't know how to resolve these warnings. --- Quote End --- The simplest and least problem clock divider is a PLL. A logic based clock divider can cause lots of timing problems as you can get a lot of skew on it. A PLL is almost always the simplest and best solution (not least as the constraints come for free with the derrive_pll_clocks SDC command)
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OK, I'll try that but I have not the time today.
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