We have made a design with a virtual jtag instance for a stratix 10 FPGA production part. While performing virtual dr shifts we have been seeing unexpected instant feeback behavoir. It seems as though the dr shift instantly comes back to me with four less bits of data when my design should be sending me completely unrelated data of that which I sent in. Has anyone else experienced this or might know what is going on?
i see quite a while has passed since you've posted that. have you found a solution? i'm pretty interested to find out as i have a similar problem. thanks https://delicerecipes.com/baked-cheesy-zucchini-casserole/
I was never able to get virtual jtag to work. I did a work around. I created my own component within qsys. The component consisted of an Avalon slave and a conduit that I would export to my designs. Within the verilog code for the component I just created an inferred memory block and had logic designating when the Avalon_master or the design could read and write from the memory block. It has worked well. It communicates through the SDM over the JTAG to Avalon master bridge which means it has a lot of over head to reading and writing so the more words you do at a time the more data you can write or read off of it per second.