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I have created a project in quartus prime pro 23.4 ant I have used clock control intel FPGA IP as a MUX for clock.And When I run synthesis error encouted.
Error(13224): Verilog HDL or VHDL error at clk_mux_stratix10_clkctrl_2000_yem6tmi.v(67): index 1 is out of range [0:0] for 'clkselect'
And sorry my computer cannot upload any picture
Below is the detail part of clk_mux_stratix10_clkctrl_2000_yem6tmi.v module module
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Dupe post.
Answered in your other post that clkselect is single bit but you're using it as 2 bit.
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Thanks, I know what this message means , but this V file is automatically created by QUARTUS prime ,which is why i am confused
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As mentioned above, the input clkselect should be 1bit while you defined it as 2 bit.
Thanks,
Ethan
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Thanks, I know what this message means , but this Verilog file is automatically created by Quartus prime ,which is why i am confused
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How are you generating this? Is it from the IP? Show your IP parameter editor settings. If it's from an IP, the GUI would prevent you from using illegal values.
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So if you regenerate the IP (Generate HDL), you keep getting the same incorrect HDL from the tool?
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Yes, I do regenerate the IP and only get the same result
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