conflicting entity names between TestBench and DUT in ModelSim

[Altera_Forum]

Using Quartus II, I generated an .vho (gate level netlist) with option "maintaining hierarchy" set to on.  

 While in the process of simulating the design, I'm getting binding for component instance errors since my testbench called out some entities that have the same names as the design (DUT) in the gate level netlist.    Is there a way to separate them where each (testbench and DUT) obtain its respective component but then bring it all together on the testbench for simulation in ModelSIM?

[Altera_Forum]

You could compile your DUT into one work library and your testbench components into another. 

 Your top-level testbench would then reference both

[Altera_Forum]

Update: I capture the stimulus input in a VCD (vector change dump file) and got rid of the testbench. That seem to be working for this issue