counting input signals

[Altera_Forum]

hello there, 

I'm quite new to the fpga world, and i have run into a problem. The idea is that I want to count incoming impulses on pin1 per second (frequency varies from 200~ to 1000hz) , and then display that number on a 7segment display.  Im using the schematic layout thing.   1.I made a counter, that converts 50Mhz onboard clock to 1Hz signal.  2.A second counter (10bit) counts the impulses on pin1, and resets when it receives aclr signal ( the 1Hz signal)  3.A latch, that allows data to flow through when it receives the same 1Hz signal. aswell as a bcd converter to display the numbers.  Now the problem is clock skew > data delay. failed paths.. why oh why does this happen. I think that quartus somehow thinks of my pin1 signals as a second clock or something. What can i do ?

[Altera_Forum]

Maybe you'd better post your schematic.

[Altera_Forum]

Here goes nothin: 

  module tau( input clk, output reg Hz); reg cnt; always @(posedge clk) begin if (cnt == 50000000) begin cnt <= 0; Hz <= 1; end else begin cnt <= cnt+1; Hz <= 0; end end endmodule module bcd( input data, output reg seg); reg z; integer i; always @(posedge data) begin z = 0; z = data; for (i=0; i <= 6; i = i+1) begin if (z > 4) z = z + 3; if (z > 4) z = z + 3; if (z > 4) z = z + 3; z = z; end seg=z; end endmodule module leddisplay(data, A1, B1, C1, D1, E1, F1, G1); input data; output wire A1, B1, C1, D1, E1, F1, G1; reg first; reg Sevenseg1; always @(posedge data) begin first <= data; case(first) 4'b0001: Sevenseg1 = 7'b0000110; //1 4'b0010: Sevenseg1 = 7'b1101101; //2 4'b0011: Sevenseg1 = 7'b1111001; //3 4'b0100: Sevenseg1 = 7'b0110011; //4 4'b0101: Sevenseg1 = 7'b1011011; //5 4'b0110: Sevenseg1 = 7'b0011111; //6 4'b0111: Sevenseg1 = 7'b1110000; //7 4'b1000: Sevenseg1 = 7'b1111111; //8 4'b1001: Sevenseg1 = 7'b1110011; //9 default: Sevenseg1 = 7'b0000000; endcase end assign {A1,B1,C1,D1,E1,F1,G1} = Sevenseg1; endmoduleLeddisplay obviously only shows one digit, but ignore that.    Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew  Info: Detected ripple clock "lpm_latch0:inst2|lpm_latch:lpm_latch_component|latches[0]" as buffer  Info: Detected ripple clock "bcd:inst3|seg[0]" as buffer  Info: Detected ripple clock "tau:inst1|Hz" as buffer

[Altera_Forum]

Well, it's pretty clear from the schematic that "inputs" is being used as the clock signal to lpm_counter0. 

So, that part is pretty straightforward.  In your "bcd" and "leddisplay" have a weird sensitivity list: always @ (posedge data). I'm not sure this behaviour can actually be mapped into hardware, since data is a bus, not a signal.  And in any case, it's not what you want. With this code, the output's will only change when one of the "data" bits goes from 0 to 1, but not the other way arround. You problably want to use always @ (*) to describe combinational logic.  Finally, I advise against using latches in FPGAs as much as possible. Use a flip-flop with a clock enable.

[Altera_Forum]

Thanks for the answer. I will try the "always @ (*)" .  

 Can a flip-flop be used for a data stream ? I suppose i need a way to only work with the final sum of the impulses

[Altera_Forum]

I don't quite understand the question.

[Altera_Forum]

well, i need to count up the impulses, and then work with that number(display it, maybe add something, etc). 

From what i know, a flip-flop can store only 1 bit of information (My understanding can be wrong here). In this case I have 10bits worth of data, that i have to pass to the bcd each second.   Maybe you could post a code, or something like that. I would really appreciate it!

[Altera_Forum]

Ah, I understand your doubt now. 

Well, both an elementary latch and a flip-flop store just a single bit.  The lpm_latch0 element you have in your design is an array of 10 latches. My suggestion was to replace it with an array of 10 flip-flops.

[Altera_Forum]

Got it! 

Is there a preset element in the schematic builder for that?

[Altera_Forum]

I am clueless regarding schematic (I always used HDL).

[Altera_Forum]

ok I also got it

[Altera_Forum]

--- Quote Start ---  Got it! Is there a preset element in the schematic builder for that?  --- Quote End ---    Hi,  such elements are available. You have two choices :  1. When you double click in your schematic a windows opens. On the left side you couls see a folder called : ....../libraries. Under the subfolder "primitives" you find a folder "storage". There you can select "dff" for a register and place the symbol in your schematic. When you connect the register to a bus Quartus recognice the number of register automatically.  2. You can use the Megawizard Plug-in Manager:  Under Tools choose "Megawizard Plug-in Manager". Under Storage choose LPM_FF and go through all the tabs. The Megawizard generates a symbol for the register. Again double click into your schematic. You will find the symbol foe the register in the folder "Projec  t".  Kind regards  GPK

[Altera_Forum]

Thanks! I'll try that asap

[Altera_Forum]

Awesome, everything works! thank you so much. 

 Now maybe somebody could tell me how to control a 7 segment led display? I don't understand how to select and controls pins, so that they would act as GND when I need them to?