create_clock .sdc syntax

[Altera_Forum]

Hi, 

 I am trying to specify a period constraint to input_clk[1] port of a PLL.   Every example I can find shows:    create_clock -period 10.000 -name clk [get_ports {clk}]    The issue is that I have two PLLs which have the same port names.. so how do I modify the [get_ports{clk}] parameter to specify a specific PLL port?   I've tried including a specific instance name but TA barfed... Any ideas?   thx

[Altera_Forum]

From what I understand, ports are a top-level entity concept from the timing analyzer's perspective. So, when you refer to [get_ports {clk}], the timing analyzer is looking for an I/O port on your top-level entity called clk. Ports of internal instances, like your PLL, are pins from the timing analyzer's perspective. In order to create a clock on your PLL input source, you can either create the clock on the T/L entity port using the syntax you described or you can create the clock on the PLL instance port/pin using something like [get pins {<hierarchical_path_to_pll>/<pll_clk_pin>}].

[Altera_Forum]

--- Quote Start ---  Hi,   I am trying to specify a period constraint to input_clk[1] port of a PLL.   Every example I can find shows:    create_clock -period 10.000 -name clk [get_ports {clk}]    The issue is that I have two PLLs which have the same port names.. so how do I modify the [get_ports{clk}] parameter to specify a specific PLL port?   I've tried including a specific instance name but TA barfed... Any ideas?   thx  --- Quote End ---    Hi,  have look to the small attached project. Maybe it will answer your question.  Kind regards  GPK