creating .pof file

[Altera_Forum]

Hi all, 

I am using a CycloneIII FPGA. When I compile my design, only a .sof file is created but not a .pof file. What should I configure in order to create a .pof file (for Active Serial Programming)?  Thanks, Dvido

[Altera_Forum]

--- Quote Start ---  Hi all, I am using a CycloneIII FPGA. When I compile my design, only a .sof file is created but not a .pof file. What should I configure in order to create a .pof file (for Active Serial Programming)?  Thanks, Dvido  --- Quote End ---    Hi Dvido,  you can convert the sof to a pof file. Open Quartus and choose:  File -> Convert Programming Files   Kind regards  GPK

[Altera_Forum]

Actually I noticed that it's a part of a bigger problem. 

As I understand, these files are supposed to be created by default. Except that, when I compile a design, sometimes the compiler won't give me an error on some basic things, like wrong vector size (things that would always result with a compilation error). I re-installed QuartusII but it didn't help. Any ideas?

[Altera_Forum]

Dear Divdo and others 

Greetings May I ask for your help, please? I am compiling my design by using Cyclone II. The compilation was successfully done and yet to get .pof and .sof files. Kindly advise me what I should do?   Regards   nazar

[Altera_Forum]

--- Quote Start ---  Actually I noticed that it's a part of a bigger problem. As I understand, these files are supposed to be created by default. Except that, when I compile a design, sometimes the compiler won't give me an error on some basic things, like wrong vector size (things that would always result with a compilation error). I re-installed QuartusII but it didn't help. Any ideas?  --- Quote End ---     Hi Dvido,  did Quartus finished succesfully or not ? Maybe you can post an example here ?  Kind regards  GPK

[Altera_Forum]

It did, though it had a problem with one of the files (don't remember which one) so I deleted all the compilation files and re-compiled. Also when I burn it it works fine. I converted the files like you suggested.  

I still think that I have a problem since these files aren't generated automatically and the compiler acts a little strange (as I described earlier).

[Altera_Forum]

--- Quote Start ---  It did, though it had a problem with one of the files (don't remember which one) so I deleted all the compilation files and re-compiled. Also when I burn it it works fine. I converted the files like you suggested.  I still think that I have a problem since these files aren't generated automatically and the compiler acts a little strange (as I described earlier).  --- Quote End ---    Hi,  that means all is up and running now?  Kind regards  GPK

[Altera_Forum]

I am able to compile but I still have these strange issues with the .pof files not being created and some errors not being reported by the compiler.

[Altera_Forum]

--- Quote Start ---  I am able to compile but I still have these strange issues with the .pof files not being created and some errors not being reported by the compiler.  --- Quote End ---     Ok,  when using a pof file you need a configuration device. In the Quartus default settings the generation of prog files for the configuration device is disabled ( I don't know why ??). You can change the setting by:  Assignments -> Device -> Device and Pin Options ... -> configuration   Switch on "Use Configuration Device" and select your configuration device.  For your other problem, can you post an example ?  Kind regards  GPK

[Altera_Forum]

Here is an example of the strange behavior: bellow you can find a very simple process. It didn't work yesterday but its working today, though I haven't changed anything. 

 handshake : process (rst,gpio14)  begin  if (rst = '0') then  start_handshake_fsm <= '0';  temp_counter <= (others => '0');  elsif (gpio14'event and gpio14 = '1') then  if (temp_counter < "1000") then  temp_counter <= temp_counter + '1';  start_handshake_fsm <= '0';  elsif (temp_counter = "1000") then  temp_counter <= temp_counter;  start_handshake_fsm <= '1';  end if;  end if;  end process handshake;

[Altera_Forum]

--- Quote Start ---  Here is an example of the strange behavior: bellow you can find a very simple process. It didn't work yesterday but its working today, though I haven't changed anything.  handshake : process (rst,gpio14)  begin  if (rst = '0') then  start_handshake_fsm <= '0';  temp_counter <= (others => '0');  elsif (gpio14'event and gpio14 = '1') then  if (temp_counter < "1000") then  temp_counter <= temp_counter + '1';  start_handshake_fsm <= '0';  elsif (temp_counter = "1000") then  temp_counter <= temp_counter;  start_handshake_fsm <= '1';  end if;  end if;  end process handshake;  --- Quote End ---    Hi,  what kind of strange behaviour did you observe ? Do have timing violations in your design ? Where does the gpio14 signal coming from ( xxMhz?)  Kind regards  GPK

[Altera_Forum]

The strange behavior is that it didn't work and then suddenly it started working.  

gpio14 is coming from another FPGA with a very low frequency, there shouldn't be any timing issue since I don't use the clock for that process.  I ran it now for a few times and it works fine.

[Altera_Forum]

--- Quote Start ---  The strange behavior is that it didn't work and then suddenly it started working.  gpio14 is coming from another FPGA with a very low frequency, there shouldn't be any timing issue since I don't use the clock for that process.  I ran it now for a few times and it works fine.  --- Quote End ---    Hi,  but you use the gpio14 as a clock ! (gpio14'event and gpio14 = '1'). If you use signals generated in this block in a block with a different clock your design will not work stable. BTW did you connect yor reset signal ?  Kind regards  GPK

[Altera_Forum]

Hi, 

I use the start_handshake_fsm signal only as a flag for another process. Though the other process uses another clock, it doesn't matter. As I said now its working. I did connect the reset signal. Might be that the FPGA was "stuck" and when I switched the power off for the night it fixed it?

[Altera_Forum]

--- Quote Start ---  Hi, I use the start_handshake_fsm signal only as a flag for another process. Though the other process uses another clock, it doesn't matter. As I said now its working. I did connect the reset signal. Might be that the FPGA was "stuck" and when I switched the power off for the night it fixed it?  --- Quote End ---     Hi,  how did you synchronize your handshake signal in the other clock domain, in order to prevent metastability ? That could be the reason why your design is stuck .  Kind regards  GPK

[Altera_Forum]

Hi, 

I put an if condition on the other process: if (rising_edge(clk) and start_handshake_fsm = '1') then....  is that a problem?

[Altera_Forum]

--- Quote Start ---  Hi, I put an if condition on the other process: if (rising_edge(clk) and start_handshake_fsm = '1') then....  is that a problem?  --- Quote End ---    Hi,  this could be a problem. I assume that "clk" is much faster then the gpio signal.  In this case you should latch the handshake signal with two registers in a row clocked by "clk". For more info's look:  http://www.fpga4fun.com/crossclockdomain1.html  Kind regards  GPK