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declaring objects in verilog

Altera_Forum
Honored Contributor II
‎07-16-2015 11:54 AM
1,253 Views

sorry wrong post

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Altera_Forum
Honored Contributor II
‎07-16-2015 05:40 PM
517 Views

You are looking for signals in a submodule bfm_common that is never called or defined.

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