defparam issue vqm

[AEsqu]

Hello,

I face a new issue with Quartus prime pro (together with a .vqm from Synplify), I did not have this issue with Quartus 13.1 (same RTL code) for the stratix 3. What shall I do?

RTL Module:

module rng4_sa_intg #(
APB_WIDTH = 12
) (

// FPGA Clock
`ifdef ID_CFG_DTRNG_FPGA // FPGA support
input logic ip_fpga_ringo_clk,
`endif // ID_CFG_DTRNG_FPGA // FPGA support

input logic clk_and_reset_p_pclk,
input logic clk_and_reset_p_rstn,
...

Instantiation in RTL (black box in that project, the rng4_sa_intg is in another .vqm)

rng4_sa_intg #(
.APB_WIDTH(12)
) u_trng (

`ifdef ID_CFG_DTRNG_FPGA // FPGA support
.ip_fpga_ringo_clk (free_running_48mhz_clk),
`endif // ID_CFG_DTRNG_FPGA // FPGA support

.clk_and_reset_p_pclk (rng_apb_clk),

.vqm content (stratix10_fpga_a_mix.vqm):

rng4_sa_intg u_trng (
.ip_fpga_ringo_clk(free_running_48mhz_clk),
.clk_and_reset_p_pclk(rng_apb_clk),
...
.test_p_async_disable(GND)
);
defparam u_trng.APB_WIDTH=12;
// @1005:9418

other .vqm with the rng4_sa_intg block (rng4_sa_intg_stratix10.vqm):

/* Synopsys
.origName=rng4_sa_intg
.langParams="APB_WIDTH"
APB_WIDTH=12
*/
input ip_fpga_ringo_clk ;
input clk_and_reset_p_pclk ;

.....

Using Synplify R-2021.03 + patch.

 
Quartus prime pro 21.1.0 error:

Error(14394): Verilog HDL error at stratix10_fpga_a_mix.vqm(3013071): APB_WIDTH is not declared under the prefix "u_trng"
Error(16186): Can't elaborate top-level user hierarchy

I use in the .qsf:

set_global_assignment -name VQM_FILE ../../rng4_sa_intg/synplify/synthesis/rng4_sa_intg_stratix10.vqm
set_global_assignment -name VQM_FILE ../../stratix10/synplify_synth_quartus_fit/synthesis/stratix10_fpga_a_mix.vqm

Kind Regards,

Alex.

[SyafieqS]

From the error message, the issue is probably due Quartus not recognizing the parameter APB_WIDTH in the instantiation of the rng4_sa_intg module.

Few steps to narrow down and solve it:

1. Check the syntax of the instantiation in stratix10_fpga_a_mix.vqm and ensure that the parameter is spelled correctly and in the correct location. It should be in the parentheses following the module name:

rng4_sa_intg u_trng (

  .ip_fpga_ringo_clk(free_running_48mhz_clk),

  .clk_and_reset_p_pclk(rng_apb_clk),

  ...

);

defparam u_trng.APB_WIDTH=12;

2. Ensure that the rng4_sa_intg module is correctly included in the Quartus project 

3. Try generating a new .vqm file with the latest version of Synplify and see if the issue persists.

[AEsqu]

1. Yes, as mentioned in the original question:

.vqm content (stratix10_fpga_a_mix.vqm):

rng4_sa_intg u_trng (
.ip_fpga_ringo_clk(free_running_48mhz_clk),
.clk_and_reset_p_pclk(rng_apb_clk),
...
.test_p_async_disable(GND)
);
defparam u_trng.APB_WIDTH=12;
// @1005:9418

2.Yes, as mentioned in the original question (I just added _stratix10 at the end compare to original stratix 3 version):

(set_global_assignment -name VQM_FILE ../../rng4_sa_intg/synplify/synthesis/rng4_sa_intg_stratix10.vqm)

content:

// VQM4.1+
module rng4_sa_intg (
ip_fpga_ringo_clk,
clk_and_reset_p_pclk,
...
test_p_async_disable
)
;

/* Synopsys
.origName=rng4_sa_intg
.langParams="APB_WIDTH"
APB_WIDTH=12
*/
input ip_fpga_ringo_clk ;

...

3. Will try now. Edit: Same result with version T-2022.09

[AEsqu]

Hi,

I would like Quartus to print a message when it reads a source RTL file (similar to what Quartus 13.1 does by default).

I want to make sure it really reads the rng4_sa_intg_stratix10.vqm file as described in the .qsf.

Because if it does not, this is the root cause of the problem.

I changed the HDL level from 2 to 3 but that has no impact on the verbosity messages.

[AEsqu]

This is only what I see at the moment:

[AEsqu]

As a test, I replaced the vqm by the interface module,

and Quartus goes further and does not complain about the APB_WIDTH parameter.

set_global_assignment -name SYSTEMVERILOG_FILE ../../INTERFACE/rng4_sa_intg.sv
#set_global_assignment -name VQM_FILE ../../rng4_sa_intg/synplify/synthesis/rng4_sa_intg_stratix10.vqm

So I think the rng4_sa_intg_stratix10.vqm is not even read out for some reaon.

Could it be that Quartus prime pro 21.1.0 has problem with more than one vqm (quartus 13.1 had no problem loading 2 vqm)?

[SyafieqS]

I cannot confirm this without replicate the issue.

May I know if possible for you to attach small design with one vqm and more for further investigation.

Also, is it possible for you to try this on latest release 22.4? 

[SyafieqS]

Let me know if there is any update from previous reply

[AEsqu]

Hello, I don't have a test case.

Don't you have a test case with 2 vqm files at your side?

We miss the license for version 22.x at the moment, So I cannot test.

[SyafieqS]

I need the design that is produce by user to replicate the exact issue. Can we have a quick call on this if possible?

[AEsqu]

I will try to create a small test case.

Basicaly we need 2 vqm and a parameter in one vqm.

[SyafieqS]

Hi,

Noted. Let me know any update on this.

[AEsqu]

Hello,

I was able to create a small test case with 2 vqm.

One is with the stratix 3 (which works fine)

and one with the stratix 10 (which fails).

Same version of Synplify is used.

Quartus 13.1 is used for the stratix 3,

quartus 22.1 pro is used for the stratix 10.

I have a .tgz file which contains the input rtl code, the synplify projects, the vqm's and the quartus projects.

Please tell me how to send this file in private.

Alex.

[SyafieqS]

Please reply to my email to send it

[AEsqu]

I have replied to your email, let me know if you received it.

[SyafieqS]

I did not receive your email. I am sending something to your email.

[AEsqu]

I replied to your personal email.

[AEsqu]

Hello,

Are you inspecting the provided test cases at your side?

Alex.

[SyafieqS]

I have replied to your email. I create a ftp for you to upload the file.

I will take a look.

Let me know any concern on this.

[SyafieqS]

I was on long public holiday and will take a look at the design.

Will update you.

[SyafieqS]

Alex,

How urgent this issue is?

Does it roadblock you development?

I am checking this with engineering team