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degedge count problem..

Altera_Forum
Honored Contributor II
‎06-10-2017 01:56 PM
1,499 Views

Hi, I have a very simple verilog code. But I get wrong result. When I look through the oscilloscope, I see 10 negative edges. But the result I get with a simple code that I write is sometimes 12, sometimes 13 or even more. The yellow graphic is scl.. 

 

reg[15:0] scl_clock_count=0; 

always @(negedge scl) 

scl_clock_count <= scl_clock_count + 1'b1;
multiple-attachments.zip
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Altera_Forum
Honored Contributor II
‎06-10-2017 05:53 PM
648 Views

What is SCL? is it the clock from an SPI bus? for this, usually it is safer to use a fast system clock and sample the SCL with the fast system clock.

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