different behavior for the same project after synthesis&compile

[lambert_yu]

Hi all,

     I face one strange problem:

     For the same project, use the same quartus software, but after synthesis & compile, I got some .jic file, but for some .jic, the behavior is abnormal on board.

     In this project, there is transceiver, ddr and so on, for the abnormal .jic file, the output of transceiver is not correct though reset or re-poweron; After next syntheis & compile, the output of transceiver is correct. For these .jic, there is no timing slack whithin this part (transceiver & ddr), so I want to make sure which causes this problem, could someone hlep me?

  fpga : 10ax115n2f45e1sg

  quartus : pro 16.0

Brs,

Lambert

[sstrell]

Without seeing any results or a project or any design files or the exact steps you've followed, there's not much that can be done here.  Supply some more information on exactly what is going on and maybe some files or code or something.

[lambert_yu]

Hi，

      About company's confidentially principle, I could not provide any RTL code. About Compile flow : follow analysis&synthesis -> fitter->assembler->timequest;  I make sure that the RTL is same and most of .jic file can run normally on debug board, some .jic file is not okay.

[sstrell]

OK, but without posting any of the design or compiler messages or timing reports (working and non-working) or any information at all, nobody can really help you.