Is there a way to connect two components other than manually drawing wires between them? Like a certain button combination will connect two components with a wire automatically?
I expect ,too.As far as I concerned, I don't know other ways to connect componets without manually drawings. Is there any uncomfortable feelings with it?:) Maybe it takes much your time, but the procedure is important for your redesign.
I'm going to assume you're using the schematic design tool here. If you use an HDL language using the same signal name will automatically connect two signals. I haven't used the schematic tool in a long time but it used to work that if you draw a dangling net, or bus, off a component pin and give it the same name as another dangling net, or bus, the connection would be automatically made. Note that it won't, or didn't, draw a line between the two but did connect via naming attribute.
It is indeed as Bobf said. If you use Vhdl, you can also use "map" sentence to connect two different signals, pins, and ports.I always use vhdl and find it well. How about posting an example about the use of HDl language, which the same signal names could be connected automatically. Thanks.
If I've done this right I've added an attachment VHDL file named new_test_top.vhd.It is a top level design with a reasonably good example of combining lower level designs together, it even includes a call to an EPLL and some top level code. It's a pretty basic example of hierarchical designing in VHDL. Most of the COMPONENTs are user generated lower level designs. For all the signals that are to interface to other COMPONENTs you declare them as SIGNALs. For the SIGNALs that are inputs or outputs they are called such at the top-level ENTITY. For those SIGNALs that both go to outputs and to other COMPONENTs you must rename something and direct them appropriately. As you can see I tend to follow a rather strict formatting of my code to try and make it easier to follow. You don't need to follow such a strict format, you just need to follow the allowed VHDL coding rules. I hope you can get this.