error:Port "enable" does not exist in primitive "latch" of instance "u0"

[Altera_Forum]

When i was simulating my VHDL coding in Quartus II web edition i am getting the following errors: 

Error:Port "enable" does not exist in primitive "latch" of instance "u0" Error:can't elaborate user hierarchy "lut_0:06"  But it's working well in the modelsim-altera software.  I need the soln then only i can implement it in DE1 board.  Thanks in advance.

[Altera_Forum]

Show the code. 

 What do you mean with "simulating my VHDL coding in Quartus II web edition" different from using modelsim-altera?

[Altera_Forum]

this is just part the coding, 

  library ieee;  use ieee.std_logic_1164.all;      entity lut_0 is  port( a,b,c,d : in std_logic;  i0 : in std_logic:='0';  i1 : in std_logic:='1';  i2 : in std_logic:='0';  i3 : in std_logic:='1';  i4 : in std_logic:='1';  i5 : in std_logic:='0';  i6 : in std_logic:='0';  i7 : in std_logic:='1';  i8 : in std_logic:='1';  i9 : in std_logic:='0';  i10 : in std_logic:='0';  i11 : in std_logic:='1';  i12 : in std_logic:='1';  i13 : in std_logic:='0';  i14 : in std_logic:='1';  i15 : in std_logic:='0';  enable : in std_logic;  FA : inout std_logic );  end lut_0;      architecture ar of lut_0 is    component latch  port( d : in std_logic;  enable : in std_logic;  q : out std_logic );  end component;    component sel_fa_0  port( a,b,c,d : in std_logic;  l0,l1,l2 : in std_logic;  l3,l4,l5 : in std_logic;  l6,l7,l8 : in std_logic;  l9,l10,l11 : in std_logic;  l12,l13 : in std_logic;  l14,l15 : in std_logic;  Output : out std_logic );  end component;      signal w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15 : std_logic;    begin    u0: latch port map(i0,enable,w0);  u1: latch port map(i1,enable,w1);  u2: latch port map(i2,enable,w2);  u3: latch port map(i3,enable,w3);  u4: latch port map(i4,enable,w4);  u5: latch port map(i5,enable,w5);  u6: latch port map(i6,enable,w6);  u7: latch port map(i7,enable,w7);  u8: latch port map(i8,enable,w8);  u9: latch port map(i9,enable,w9);  u10: latch port map(i10,enable,w10);  u11: latch port map(i11,enable,w11);  u12: latch port map(i12,enable,w12);  u13: latch port map(i13,enable,w13);  u14: latch port map(i14,enable,w14);  u15: latch port map(i15,enable,w15);

[Altera_Forum]

Apparently a different entity with the name "latch" but other port names exists in your library. 

 There's e.g. a latch in altera_primitives_components.vhd. It's better to avoid ambiguous names like this.

[Altera_Forum]

Thanx...I changed the latch entity name..now that error is not coming... 

 But now i am getting the following Error: Can't place 1545 pins with 3.3-V LVTTL I/O standard because Fitter has only 311 such free pins available for general purpose I/O placement  I am having Altera Cyclone II board..In my design i used 1545 I/O pins but Cyclone II only hav 311 pins.... any soln for this ...to check my design in the FPGA board... reply me ASAP..

[Altera_Forum]

what have you got at the top level? 

Basically, the only solution is to use many many fewer pins (or get a buigger device, but I dont think there is one with 1545 IOs. Not even a Stratix 5)