exclude module from timing synthesis

[Altera_Forum]

Hi all!, 

I want to exclude one module from the timing synthesis so that the good wires are reserved for the rest of the program, which is more timing critical.  The specific module is instantiated as inst1 and called in another module instantiated as inst0.   Do the following declarations of false paths in the sdc-file do the trick?  set_false_path -from [get_pins {inst0|inst1|*}] -to [get_registers *] set_false_path -from [get_pins {inst0|inst1|*}] -to [get_pins *]   Thanks, David

[Altera_Forum]

I believe your idea is wrong in the first place. All logic must pass timing on its clock. There is no concept of one section being more important than another. A module may be deconstrained if say multicycle can be applied. If you are failing timing on some paths fixed from build to build then you better tackle that directly. If the paths migrate from build to build then you may have reached the limit of your design/device.

[Altera_Forum]

Thanks for your answer. 

I think in my case it makes sense to exclude one module, because this module is a research-style asynchronous module with delay lines, where I don't care about the timing (its timing is messed up anyway, because Quartus cannot handle these kinds of designs).  Is there a way to exclude all logic from one module from the timing synthesis?   I believe that the way I proposed in my first message does not work.

[Altera_Forum]

Why do you believe the first one does not work? Any easy test is to run report_timing on a path from that hierarchy and see if it gets reported. If it works, no paths should exist(although they will show up if you add -false_path to your report_timing command) 

 Note that get_pins finds the inputs/outputs on every cell, where really you don't need to apply it to combinatorially cells or anything like that. You might just do: set_false_path -from [get_keepers {inst0|inst1|*} The -to is unnecessary since you just want everything. Also know that get_keepers will use the longer naming style of |entity:instance|entity:instance|... so you need to accomodate that. Just run this directly in TimeQuest first and see if it takes and makes the paths disappear. Once you're sure it's working, add the constraint to your .sdc and compile.

[Altera_Forum]

--- Quote Start ---  Thanks for your answer. I think in my case it makes sense to exclude one module, because this module is a research-style asynchronous module with delay lines, where I don't care about the timing (its timing is messed up anyway, because Quartus cannot handle these kinds of designs).  Is there a way to exclude all logic from one module from the timing synthesis?   I believe that the way I proposed in my first message does not work.  --- Quote End ---    If your module is asynchronous and does not drive next modules and let me assume it does not have clocked registers then TimeQuest will not find any reg-to-reg path to worry about. If it has clocked registers then it has to meet timing at those paths between registers. Thus it may already be excluded by its nature. If it is driving next module then those paths across module from its input to its output may become a very long path hard to meet timing. In that case your design will fail and you shouldn't exclude them.   Anyway, my understanding of set false path is that if applied to registers then it is applied to the path in between two registers and not all the way through. I might be wrong but if true you will need to specify false path from inputs of module to outputs of module.  If your design is for research purpose then when not generate it separately using generate statement or set its clock to zero or fix its inputs to a constant. That way it should be picked up by compiler as null.

[Altera_Forum]

Thanks! 

Even after setting these false paths, I get several warnings that a wire in this module "was determined to be a clock but was found without an associated clock assignment".   Indeed, the outputs of this module are connected to the clock input of Flip-Flops to monitor the output of this asynchronous module. Also this module does not use registers.  Does this warning indicate that Quartus still tries to put timing constraints on this module? Can I get rid of this warning with a false path declaration?

[Altera_Forum]

--- Quote Start ---   Can I get rid of this warning with a false path declaration?  --- Quote End ---  You can suppress the message regarding signals being detected as a clock, but without a clock constraint. I had a similar warning from a toggle synchronizer. Here's the thread (along with code and SDC files).  http://www.alteraforum.com/forum/showthread.php?t=34767  Cheers, Dave