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Altera_Forum
Honored Contributor I
977 Views

failing.paths.rpt

After an apparent successful compile with 0 errors reported and an aocx file created, 

if one looks into the directory with log and rpt files there can be rpt files such 

as top.failing_paths.rpt, and top.failing_clocks.rpt with info such listed below. 

 

What is the significance of these rpts. Should there be a recompile with different parameters?  

If so, how would one set such parameters when aoc is being used to compile the kernels? 

 

Thanks, 

 

Dan.. 

 

 

[poz@nallatech boardtest_ts_sram_sl]$ grep Worst *fail*.rpt 

top.failing_paths.rpt:Report Timing: Found 5 setup paths (5 violated). Worst case slack is -0.556  

top.failing_paths.rpt:Report Timing: Found 5 setup paths (5 violated). Worst case slack is -0.310  

top.failing_paths.rpt:Report Timing: Found 5 hold paths (5 violated). Worst case slack is -0.019  

top.failing_paths.rpt:Report Timing: Found 5 setup paths (5 violated). Worst case slack is -0.423  

top.failing_paths.rpt:Report Timing: Found 5 setup paths (5 violated). Worst case slack is -0.221  

 

top.failing_paths.rpt:Report Timing: Found 5 hold paths (5 violated). Worst case slack is -0.056  

 

 

Clock domains failing timing 

+--------+---------------+----------------------------------------------+-----------------------+-----------------+ 

; Slack ; End Point TNS ; Clock ; Operating conditions ; Timing analysis ; 

+--------+---------------+----------------------------------------------+-----------------------+-----------------+ 

; -0.556 ; -98.123 ; board_inst|ddr3b_core_usr_clk ; Slow 900mV 100C Model ; Setup ; 

; -0.423 ; -60.327 ; board_inst|ddr3b_core_usr_clk ; Slow 900mV 0C Model ; Setup ; 

; -0.310 ; -63.934 ; board_inst|pcie|wys~CORE_CLK_OUT ; Slow 900mV 100C Model ; Setup ; 

; -0.221 ; -23.398 ; board_inst|pcie|wys~CORE_CLK_OUT ; Slow 900mV 0C Model ; Setup ; 

; -0.056 ; -10.906 ; board_inst|kernel_clk_gen|kernel_pll|outclk0 ; Slow 900mV 0C Model ; Hold ; 

; -0.019 ; -0.151 ; board_inst|kernel_clk_gen|kernel_pll|outclk0 ; Slow 900mV 100C Model ; Hold ; 

+--------+---------------+----------------------------------------------+-----------------------+-----------------+
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1 Reply
Altera_Forum
Honored Contributor I
40 Views

No need to recompile anything; the kernel will work as it is. I remember seeing a note among the known issues in the changelog of AOC or quartus about these failing paths which said we should disregard them until Altera fixes it, though I cannot find it right now.

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