fixing inferred latch

[Altera_Forum]

I got the following warning message about an inferred latch on a variable: 

 Warning (10240): Verilog HDL Always Construct warning at fifo.v(103): inferring latch(es) for variable "idx", which holds its previous value in one or more paths through the always construct   And the corresponding RTL is:   always @(posedge clk or negedge resetn)  begin  if (~resetn)  begin  for (idx=0; idx<2; idx=idx+1) mem[idx] <= {(WIDTH){1'b0}};   end  else if (wr)   begin  mem[wr_ptr] <= inp_data;   end  end   How can I go about fixing this? Quartus doesn't seem to provide further information beside the warning message. Where can I find more information on this inferred latch (perhaps from a netlist or latch instantiation logfile from the synthesizer)?   Thanks!

[Altera_Forum]

You didn't show the definition of idx, it may be the reason for the warning. In my opinion, the warning isn't reasonable regarding the shown code snippet. A for loop index variable can't infer a latch. idx should have integer type, normally. 

 As another point, I think, it's no good idea to use an asynchronous reset of a FIFO memory, because it blocks possible RAM inference.

[Altera_Forum]

The warning can be completely ignored. Quartus has given this message for years. I told Altera about it a long time ago and I guess they haven't done anything about it. The message is given during synthesis. Basically the compiler is looking at idx as an actual piece of logic rather than a simple loop iterator in the language. If you look at the final compiled RTL though, you will find no instance of "idx" anywhere. Just ignore it. 

 Jake

[Altera_Forum]

How can I check to see if "idx" exists in the final compiled RTL? Thanks!

[Altera_Forum]

You can use the RTL viewer. Any attempt to find "idx" will turn up nothing. The variable "idx" never actually makes it into the netlist. 

 If you right click on the warning message and click "Help" you'll get the help info for the warning message. Part of the help file says the following:   --- Quote Start ---   In some cases, you may receive this warning unexpectedly. These unexpected, and sometimes false, warnings occur because Quartus II Integrated Synthesis does not eliminate false paths prior to checking for potential combinational loops.  --- Quote End ---    Jake

[Altera_Forum]

Since we get the inferred latch warnings at over a hundred places in our design, instead of going through the RTL Viewer to check every warning, is there maybe a text-version of the netlist which we can check and parse for any latch instantiation? i.e. What are the input data files read by the RTL Viewer GUI.

[Altera_Forum]

If the above code is exactly what you compiled, you get the warning for a for loop index variable. It would never create a register or latch by Verilog specification. It's different from the possible false warnings addressed by the above quoted Quartus help file. 

 My experience with Quartus VHDL compiler says, that "inferred latch" warnings are mostly correct, indicating intended or unintended asynchronous latches. I'm only occasionally coding Verilog, but I didn't yet notice extensive false warnings.