Re: flop-flop simulation in ModelSim

Altera_Forum · ‎05-17-2018

i try to simulate [1:0]flip-flop in ModelSim and i see one normal signal(out_inf[0]) and one blue signal(out_inf[1]). What is it?

Altera_Forum · ‎05-17-2018

Blue means 1'bZ. We will need to code to understand the problem.

Altera_Forum · ‎05-17-2018

dff code


module dff(clk, din, dout); 
  input clk; 
  input  din; 
  output  dout; 
reg dout; 
 always @ (posedge clk) 
  begin 
   dout <= din; 
end 
endmodule

testbench


module top; 
   reg clk; 
   reg  in_inf; 
   wire  out_inf;
dff D1 (clk, in_inf, out_inf); 
initial // Clock generator
  begin
    clk = 0;
    forever# 10 clk = !clk;
  end
initial //in_inf    
  begin
    in_inf = 0;
   # 28 in_inf = 1;
   # 5 in_inf = 0;
  end
initial    //in_inf    
  begin
    in_inf = 0;
   # 48 in_inf = 1;
   # 5 in_inf = 0;
  end
endmodule

i want to see normal (not blue) signal as out_inf[1]

Altera_Forum · ‎05-17-2018

You should always look sharp at the Modelsim warnings. They tell about problem with reg dout declaration. Must be reg [1:0] dout. Or include reg in the output definition.

Altera_Forum · ‎05-17-2018

whys out_inf[0] is h'x (in the beginning), not zero?

Altera_Forum · ‎05-18-2018

Because you dont have an initial or reset value for them. They wont be assigned a value until the first clock

Altera_Forum · ‎05-18-2018

can i initialize value before first clock?