help!!

[Altera_Forum]

I'm creating a code now, which i need to increase the input A,B by 2 after each state.  

Example  @s0: A=00000001, B=00000010.  @s1: I want A= 00000011 and B= 00000100. How do i do it?   And i know there's something wrong with my code, highlighted in red. As i need help for this. Can someone help?  This is code.    library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.All;   -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;   -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;   entity Project3M2A is  Port ( A : in STD_LOGIC_VECTOR (7 downto 0);  B : in STD_LOGIC_VECTOR (7 downto 0);  W : out STD_LOGIC_VECTOR (7 downto 0);  X : out STD_LOGIC_VECTOR (7 downto 0);  Y : out STD_LOGIC_VECTOR (7 downto 0);  Z : out STD_LOGIC_VECTOR (7 downto 0);  LOAD : in STD_LOGIC;  RST : in STD_LOGIC;  CLK : in STD_LOGIC); end Project3M2A;   architecture Behavioral of Project3M2A is     type state_type is (S0,S1,S2);--,S3,S4,S5,S6,S7,S8,S9,S10); signal state, state_next: state_type; signal add1_op0,add1_op1,add2_op0,add2_op1: signed ( 16 downto 0); signal mult_op0,mult_op1: signed (16 downto 0); signal R1,R2,R3,R4,R5,R6: signed (7 downto 0 );--R3,R4,R5,R6: std_logic_Vector (7 downto 0 ); --signal R5,R6,R7,R8,R9,R10,R11,R12: std_logic_Vector (7 downto 0 ); signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next: signed( 7 downto 0);--,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: std_logic Vector( 7 downto 0); signal prod: signed (33 downto 0); begin     P1: process(clk,rst) is  begin  if rst='0' then  state<=S0;  r1 <= (others => '0');  r2 <= (others => '0');  r3 <= (others => '0');  r4 <= (others => '0');  r5 <= (others => '0');  r6 <= (others => '0');  --r7 <= (others => '0');  --r8 <= (others => '0');  --r9 <= (others => '0');  --r10 <= (others => '0');  --r11 <= (others => '0');  --r12 <= (others => '0');  --r6 <= (others => '0');  --r7 <= (others => '0');  elsif(clk'event and clk='1') then   state <=state_next; -- next state update  r1<=r1_next;-- update next state at rising edge of clk  r2<=r2_next;  r3<=r3_next;  r4<=r4_next;  r5<=r5_next;  r6<=r6_next;  --r7<=r7_next;  --r8<=r8_next;  --r9<=r9_next;  --r10<=r10_next;  --r11<=r11_next;  --r12<=r12_next;  end if; end process P1; P2: process (load, state,r1,r2,r3,r4,r5,r6, A,B)  begin   r1_next<=r1;-- keep previous data if not updated  r2_next<=r2;  r3_next<=r3;  r4_next<=r4;  r5_next<=r5;  r6_next<=r6;  --r7_next<=r7;  --r8<=r8_next;  --r9<=r9_next;  --r10<=r10_next;  --r11<=r11_next;  --r12<=r12_next;  --complete<='0';  case state is  when S0 => if load ='1' then  r1_next<= signed (A(7 downto 0));  r2_next<= signed (B(7 downto 0));    state_next<=S1;  --complete<='1';  else  state_next<=S0;  end if;  when S1=>   r3_next<=signed (A(7 downto 1)& "0");  r4_next<=signed (B(7 downto 1)& "0");  state_next<= S2;  when S2=>   r5_next<=signed (A(7 downto 2)& "00");  r6_next<=signed (B(7 downto 2)& "00");  state_next<=S0;  end case;  end process p2;   end Behavioral;

[Altera_Forum]

--- Quote Start ---  Im not sure exactly what you're simulating, because your code has an error: r13_next <=signed (signed(r1_next)* signed(r2_next));  r13_next is only 8 bits. r1_next*r2_next gives a 16 bit result.  When modifed to  r13_next <=resize (r1_next* r2_next, 8);  It works just fine  --- Quote End ---      Yeah tricky, it works. But now there is a problem..  As I have highlighted in red, @S7,S8,S9. when it reaches S9, my value of R15_NEXT CHANGES, so it affects my value at S8 --> r14_next<=(r20_next+r15_next); thus affecting my S7 value of R20_next..  What can i do to not let them affect one another?   COde ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use ieee.std_logic_arith.all; --USE ieee.std_logic_signed.ALL; --USE ieee.std_logic_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Project3M2A is --generic(lower: integer:=1; upper:integer:=127); Port ( A : in STD_LOGIC_VECTOR (7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0); W : out STD_LOGIC_VECTOR (7 downto 0); X : out STD_LOGIC_VECTOR (7 downto 0); Y : out STD_LOGIC_VECTOR (7 downto 0); Z : out STD_LOGIC_VECTOR (7 downto 0); LOAD : in STD_LOGIC; COMPLETE: out STD_LOGIC; RST : in STD_LOGIC; CLK : in STD_LOGIC); end Project3M2A; architecture Behavioral of Project3M2A is type state_type is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12); signal state, state_next: state_type; --signal add1_op0,add1_op1,add2_op0,add2_op1: signed ( 7 downto 0); --signal mult1,mult2,mult3,mult4,mult5, mult6: signed (7 downto 0); signal R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14: unsigned( 7 downto 0); signal R15,R16,R17,R18,R19,R20: unsigned (7 downto 0 ); -- Registers for doing X and + signal R1_next,R2_next,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next,R13_next,R14_next: unsigned( 7 downto 0);--,R12_next,R13_next,R14_next,R15_next: signed( 7 downto 0);--,R3_next,R4_next,R5_next,R6_next,R7_next,R8_next,R9_next,R10_next,R11_next,R12_next: std_logic Vector( 7 downto 0); signal R15_next,R16_next,R17_next,R18_next,R19_next,R20_next: unsigned( 7 downto 0); --signal R13_next: std_logic_vector ( 7 downto 0); --signal prod1,prod2,prod3: signed (7 downto 0); --signal sum1,sum2: signed (7 downto 0); begin P1: process(clk,rst) is begin if rst='0' then state<=S0; r1<=r1_next;-- update next state at rising edge of clk r2<=r2_next; r3<=r3_next; r4<=r4_next; r5<=r5_next; r6<=r6_next; r7<=r7_next; r8<=r8_next; r9<=r9_next; r10<=r10_next; r11<=r11_next; r12<=r12_next; r13<=r13_next; r14<=r14_next; r15<=r15_next; r16<=r17_next; r18<=r18_next; r19<=r19_next; r20<=r20_next; elsif(clk'event and clk='1') then state<=state_next; case state is when S0 => r1_next<= unSIGNED(A(7 downto 0)); r2_next<= unSIGNED(B(7 downto 0)); state_next<=S1; when S1=> r3_next<=unsigned (A) +2; r4_next<=unsigned (B)+2; state_next<= S2; when S2=> r5_next<= unsigned (r3_next)+2; r6_next<= unsigned (r4_next)+2; state_next<=S3; when S3=> r7_next<=unsigned (r5_next)+2; r8_next<=unsigned (r6_next)+2; state_next<= S4; when S4=> r9_next<=unsigned (r7_next)+2; r10_next<=unsigned (r8_next)+2; state_next<=S5; when S5=> r11_next<=unsigned (r9_next)+2; r12_next<=unsigned (r10_next)+2; state_next<=S6; when S6 => r13_next <=resize (r1_next *r2_next,8); r14_next <= resize (r3_next*r4_next,8); r15_next <=resize (r5_next*r6_next,8); state_next<=S7; when S7 => r20_next<= (r13_next+r14_next); r16_next<= resize(r7_next*r8_next,8); r17_next<= resize(r9_next*r10_next,8); r18_next<= resize(r11_next*r12_next,8); state_next<=S8; when S8 => r14_next<=(r20_next+ r15_next); r15_next<= resize(r2_next*r7_next,8); r13_next<= resize(r4_next*r9_next,8); r16_next<= resize(r16_next+r17_next,8); r17_next<= resize(r11_next*r6_next,8); state_next<=S9; when S9 => r19_next<= resize(r1_next*r8_next,8); r13_next<= (r15_next+r13_next); r15_next<= (r16_next+r18_next); r16_next<= resize(r10_next*r3_next,8); r18_next<= resize(r12_next*r5_next,8); state_next<=S10; when S10 => r13_next<= (r13_next+r17_next); r16_next<= (r16_next+R18_next); state_next<=S11; when S11 => r16_next<= resize(r19_next+r16_next,8); complete<='1'; state_next<=S12; when S12 => COMPLETE<='1'; STATE_NEXT<= S0; complete <='0'; end case; end if; end process P1; W<= std_logic_vector(r14_next); X<= std_logic_vector(r16_next); Y<= std_logic_vector(r13_next); Z<= std_logic_vector(r15_next); end Behavioral;      test bench -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; --use ieee.std_logic_arith.all; --USE ieee.std_logic_signed.ALL; --USE ieee.std_logic_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values USE ieee.numeric_std.ALL; ENTITY Project3M2A_TBW IS END Project3M2A_TBW; ARCHITECTURE behavior OF Project3M2A_TBW IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT Project3M2A PORT( A : IN std_logic_vector(7 downto 0); B : IN std_logic_vector(7 downto 0); W : OUT std_logic_vector(7 downto 0); X : OUT std_logic_vector(7 downto 0); Y : OUT std_logic_vector(7 downto 0); Z : OUT std_logic_vector(7 downto 0); -- P : INOUT std_logic_vector(7 downto 0); LOAD : IN std_logic; COMPLETE: OUT std_logic; RST : IN std_logic; CLK : IN std_logic ); END COMPONENT; --Inputs signal A : std_logic_vector(7 downto 0) := (others => '0'); signal B : std_logic_vector(7 downto 0) := (others => '0'); signal LOAD : std_logic := '0'; signal RST : std_logic := '0'; signal CLK : std_logic := '0'; --Outputs signal W : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0); signal Y : std_logic_vector(7 downto 0); signal Z : std_logic_vector(7 downto 0); signal COMPLETE: std_logic :='0'; -- Clock period definitions constant CLK_period : time := 40ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: Project3M2A PORT MAP ( A => A, B => B, W => W, X => X, Y => Y, Z => Z, LOAD => LOAD, RST => RST, CLK => CLK ); A<="00000001"; B<="00000010"; load<=not load after 30ns; -- Clock process definitions CLK_process :process begin CLK <= '0'; wait for CLK_period; CLK <= '1'; wait for CLK_period; end process; -- Stimulus process stim_proc: process begin rst<='0'; wait for 10ns; rst<='1'; wait for 10ns; wait; end process; END;    My waveform outputhttp://www.alteraforum.com/forum/attachment.php?attachmentid=9703&stc=1

[Altera_Forum]

Well, for a start, the fundamental problem is that you are reading all of the _next values in the async process. You need to read the registers in here. (this may not be causing the problem, but it's a fundamental design flaw). 

 Do you have a drawing of the circuit ON PAPER from BEFORE you started coding? if not - why not? Im going to let you do at least some of the debugging....